Efficient estimation of dynamic power consumption under a real delay model
暂无分享,去创建一个
[1] Ibrahim N. Hajj,et al. Probabilistic simulation for reliability analysis of CMOS VLSI circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Kurt Keutzer,et al. Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[3] Sharad Malik,et al. Certified timing verification and the transition delay of a logic circuit , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[4] Sharad Malik,et al. Technology Mapping for Low Power , 1993, 30th ACM/IEEE Design Automation Conference.
[5] K. Keutzer,et al. On average power dissipation and random pattern testability of CMOS combinational logic networks , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[6] Sharad Malik,et al. Technology Mapping for Low Power , 1993, DAC 1993.
[7] Massoud Pedram,et al. PCUBE: A performance driven placement algorithm for low power designs , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.
[8] Kaushik Roy,et al. SYCLOP: synthesis of CMOS logic for low power applications , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[9] Farid N. Najm,et al. Transition density, a stochastic measure of activity in digital circuits , 1991, 28th ACM/IEEE Design Automation Conference.
[10] Carl-Johan H. Seger,et al. A bounded delay race model , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[11] Chi-Ying Tsui,et al. Technology Decomposition and Mapping Targeting Low Power Dissipation , 1993, 30th ACM/IEEE Design Automation Conference.
[12] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.