Design methodology for systematic derivation of fault-tolerant array processors

A systematic approach for mapping of iterative algorithms into fault-tolerant processor arrays is presented. The initial description of the algorithms is Fortran-like nested loops, and the restrictions of the intermediate forms such as UREs are avoided. The principles of the coordinate method are used and regular or piecewise regular arrays can be derived. The allocation and the scheduling of the computations are specified by suitable interpretation of the functionality of each loop index. New approaches are proposed for facilitating fault/defect-tolerant array processor design during the mapping process by using idle processing elements.<<ETX>>