An 8-bit systolic AES architecture for moderate data rate applications

The complexity involved in mapping an algorithm to hardware is a function of the controller logic and data path. Minimizing data path size can lead to significant savings in hardware area and power dissipation. This paper presents an implementation of a novel architectural transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. The technique divides the input word to several bytes and then traces each byte for extracting architectural transformation. The technique is applied on Advanced Encryption Standard (AES) algorithm which is non-linear in nature. Using this technique, the 32-bit AES algorithm is transformed into a byte-systolic architecture. The novelty of the technique is more pronounced around the mix column design which is the most complex part of the AES algorithm. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed to support 8-bit operations. The resulted AES architectures reuse same logic resources for key expansion and encryption/decryption. The proposed design offers moderate data rates in the range of 41Mbps for encryption and 37Mbps for decryption while utilizing 236 and 280 slices, respectively, on Xilinx Virtex II xc2v1000-6 FPGA. Comparison results show significant gain in throughput when compared with other 8-bit designs. This makes it a viable data/communication security solution for a variety of embedded and consumer electronics.

[1]  Jean-Didier Legat,et al.  Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[2]  Christof Paar,et al.  An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[3]  M. Liberatori,et al.  AES-128 Cipher. High Speed, Low Cost FPGA Implementation , 2007, 2007 3rd Southern Conference on Programmable Logic.

[4]  Kris Gaj,et al.  Very Compact FPGA Implementation of the AES Algorithm , 2003, CHES.

[5]  Francisco Rodríguez-Henríquez,et al.  AES algorithm implementation - an efficient approach for sequential and pipeline architectures , 2003, Proceedings of the Fourth Mexican International Conference on Computer Science, 2003. ENC 2003..

[6]  Tim Good,et al.  Very small FPGA application-specific instruction processor for AES , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[8]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[9]  Vincent Rijmen,et al.  The Design of Rijndael: AES - The Advanced Encryption Standard , 2002 .

[10]  S.M. Farhan,et al.  Mapping of high-bit algorithm to low-bit for optimized hardware implementation , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

[11]  Indranil Sengupta,et al.  An area optimized reconfigurable encryptor for AES-Rijndael , 2007 .

[12]  M. C. Liberatori,et al.  AES-128 cipher: Minimum area, low cost FPGA implementation , 2007 .