Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics
暂无分享,去创建一个
Chenming Hu | Sayeef Salahuddin | Sourabh Khandelwal | Juan Pablo Duarte | Asif Islam Khan | C. Hu | S. Salahuddin | A. Khan | S. Khandelwal | J. Duarte
[1] Chenming Hu,et al. Sub-60mV-swing negative-capacitance FinFET without hysteresis , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).
[2] Chenming Hu,et al. New industry standard FinFET compact model for future technology nodes , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).
[3] S. Datta,et al. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. , 2008, Nano letters.
[4] Asif Khan,et al. 0.2V adiabatic NC-FinFET with 0.6mA/µm ION and 0.1nA/µm IOFF , 2015, 2015 73rd Annual Device Research Conference (DRC).
[5] C. Hu,et al. Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation , 2011, 2011 International Electron Devices Meeting.
[6] C. Hu,et al. Circuit performance analysis of negative capacitance FinFETs , 2016, 2016 IEEE Symposium on VLSI Technology.
[7] S. Datta,et al. Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors , 2016, IEEE Electron Device Letters.