Generating new benchmark designs using a multi-terminal net model

Abstract For the development and evaluation of CAD-tools in the layout, placement, and routing of digital designs and for the evaluation of new computer hardware, a huge amount of benchmark circuits is required. Observing the lack of enough real benchmark designs for use in evaluation tools, one could consider to actually generate such benchmarks. In that case, it is very important that those synthetic benchmarks have the same characteristics as real designs. This paper describes and evaluates a new benchmark generation procedure that produces benchmarks with characteristics, similar to those of real benchmark designs. It will be shown that, in this respect, our new technique outperforms an existing method, presented by Darnauer and Dai (Proceedings of the 1996 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 1996, pp. 66–72).

[1]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[2]  Chung-Kuan Cheng,et al.  Ratio cut partitioning for hierarchical designs , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Wayne Wei-Ming Dai,et al.  A Method for Generation Random Circuits and Its Application to Routability Measurement , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[4]  Jonathan Rose,et al.  Generation of synthetic sequential benchmark circuits , 1997, FPGA '97.

[5]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[6]  T. Ohtsuki,et al.  Recent advances in VLSI layout , 1990, Proc. IEEE.

[7]  Fadi J. Kurdahi,et al.  On the characterization of multi-point nets in electronic designs , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[8]  Roy L. Russo,et al.  On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.

[9]  Nevin Kapur,et al.  Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking , 1998, Proceedings Design, Automation and Test in Europe.

[10]  Dirk Stroobandt.  Generating New Benchmark Designs for Evaluation of CAD Tools and New Computer Architectures , 1998 .

[11]  Roy L. Russo.  On the Tradeoff Between Logic Performance and Circuit-to-Pin Ratio for LSI , 1972, IEEE Transactions on Computers.

[12]  Jan M. Van Campenhout,et al.  Hierarchical test generation with built-in fault diagnosis , 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

[13]  Dirk Stroobandt,et al.  Towards an Extension of Rent's Rule for Describing Local Variations in Interconnection Complexity , 1995 .