An Effective Programmable Memory BIST for Embedded Memory

This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.

[1]  Kuen-Jong Lee,et al.  An on-chip march pattern generator for testing embedded memory cores , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Xiaogang Du,et al.  A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops , 2006, 2006 15th Asian Test Symposium.

[3]  Nilanjan Mukherjee,et al.  Full-speed field-programmable memory BIST architecture , 2005, IEEE International Conference on Test, 2005..

[4]  Andrea Costa,et al.  Programmable memory BIST , 2005, IEEE International Conference on Test, 2005..

[5]  Paolo Bernardi,et al.  Exploiting programmable bist for the diagnosis of embedded memory cores , 2003, International Test Conference, 2003. Proceedings. ITC 2003..