A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.

[1]  Andrea Baschirotto,et al.  A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter , 2009, IEEE Journal of Solid-State Circuits.

[2]  Andrea Baschirotto,et al.  Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends , 2007, IEEE Journal of Solid-State Circuits.

[3]  Chung-Chih Hung,et al.  A Wide Tuning Range G $ _{\rm m}$–C Filter for Multi-Mode CMOS Direct-Conversion Wireless Receivers , 2009, IEEE Journal of Solid-State Circuits.

[4]  Congyin Shi,et al.  A 4.2 mm$^{2}$ 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Shanthi Pavan,et al.  Active-RC Filters Using the Gm-Assisted OTA-RC Technique , 2011, IEEE Journal of Solid-State Circuits.

[6]  Jing Jin,et al.  A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Nasser Masoumi,et al.  A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers , 2011, IEEE Journal of Solid-State Circuits.

[8]  Yumei Huang,et al.  70-280 MHz 21 mW 53 dB SFDR Gm-C filter , 2010 .

[9]  Huailin Liao,et al.  Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Jan Craninckx,et al.  A 150 kHz–80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS , 2016, IEEE Journal of Solid-State Circuits.

[11]  Congyin Shi,et al.  Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Xu Cheng,et al.  High-dynamic-range programmable gain amplifier with linear-in-dB and DAC gain control , 2018 .

[13]  David D. Wentzloff,et al.  8.1 nJ/b 2.4 GHz Short-Range Communication Receiver in 65 nm CMOS , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Jianhong Xiao,et al.  UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.