Test structures and testing methods for electrostatic discharge: results of PROPHECY project
暂无分享,去创建一个
Gaudenzio Meneghesso | Paolo Pavan | Enrico Zanoni | K. Esmark | A. Gerosa | W. Stadler | X. Guggenmos | P. Pavan | K. Esmark | A. Gerosa | G. Meneghesso | E. Zanoni | W. Stadler | X. Guggenmos
[1] S. G. Beebe. Methodology for layout design and optimization of ESD protection transistors , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.
[2] S. M. Sze,et al. Physics of semiconductor devices , 1969 .
[3] A. Amerasekera,et al. Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters , 1991 .
[4] G. Notermans,et al. Pitfalls when correlating TLP, HBM and MM testing , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).
[5] D. Lin. ESD sensitivity and VLSI technology trends: thermal breakdown and dielectric breakdown , 1994 .
[6] Roberto Rivoir,et al. A method for the characterization and evaluation of ESD protection structures and networks , 1995 .
[7] Guido Groeseneken,et al. NMOS transistor behaviour under CDM stress conditions and relation to other ESD models , 1995 .
[8] Christian Russ,et al. Compact electro‐thermal simulation of ESD‐protection elements , 1994 .
[9] Ajith Amerasekera,et al. ESD in integrated circuits , 1992 .
[10] X. Guggenmos,et al. Does The Esd-failure Current Obtained By Transmissionline Pulsing Always Correlate To Human Body Model Tests? , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.
[11] E. Nowak,et al. Process and design for ESD robustness in deep submicron CMOS technology , 1996, Proceedings of International Reliability Physics Symposium.
[12] E. A. Amerasekera,et al. ESD in silicon integrated circuits , 1995 .