High level test generation using data flow descriptions

To significantly expedite the test generation process for sequential VLSI circuits, the hierarchy in the circuit descriptions should be exploited. Conventional test generators can provide tests for relatively small modules, which are typically embedded in large circuits. This paper considers test generation for complex VLSI circuits composed of many interconnected modules. In contrast to the previous approaches, the authors use high-level primitives and data flow descriptions to perform hierarchical test generation. Data flow descriptions provide the set of valid control signals to be activated for a particular data path to be active. Sequential propagation and justification of signals is carried out recursively. Results are presented based on an implementation of the algorithm in LISP on a Texas Instruments Explorer.<<ETX>>

[1]  Melvin A. Breuer,et al.  Test Schedules for VLSI Circuits Having Built-In Test Hardware , 1986, IEEE Transactions on Computers.

[2]  Reiner W. Hartenstein,et al.  The KARL/KARATE system-automatic test pattern generation based on RT level descriptions , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[3]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[4]  Jacob A. Abraham,et al.  Test Generation for Microprocessors , 1980, IEEE Transactions on Computers.

[5]  Kaushik Roy,et al.  A Novel Approach to Accurate Timing Verification Using RTL Descriptions , 1989, 26th ACM/IEEE Design Automation Conference.

[6]  Arthur D. Friedman,et al.  Logical design of digital systems , 1975 .

[7]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[8]  D. Smith,et al.  A Unified Design Representation Can Work , 1989, 26th ACM/IEEE Design Automation Conference.

[9]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[10]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .

[11]  Mark Harper Shirley.  Generating Tests by Exploiting Designed Behavior , 1986, AAAI.

[12]  Jacob A. Abraham,et al.  KNOWLEDGE BASED TEST GENERATION FOR VLSI CIRCUITS. , 1987 .

[13]  John P. Hayes,et al.  Hierarchical test generation using precomputed tests for modules , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Michael J. Bending,et al.  Hitest: A Knowledge-Based Test Generation System , 1984, IEEE Design & Test of Computers.

[15]  S. DasGupta,et al.  LSI chip design for testability , 1978, 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[16]  Jacob A. Abraham,et al.  Functional Testing of Microprocessors , 1984, IEEE Transactions on Computers.

[17]  John P. Hayes,et al.  Hierarchical test generation using precomputed testsd for modules , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.