AC performance improvement of folding/interpolation ADC with SiGe HBT

This paper describes how to improve the accuracy (the number of effective bits) of a folding/interpolation ADC for a high-frequency input signal. First we identify the AC performance limitation as being the analog timing skew between higher-bits and lower-bits of the folding/interpolation ADC. Next we show in theory and by SPICE simulation that a digital error correction with analog timing skew minimizing circuits reduces the analog timing skew problems. Then we show that using a track and hold circuit before the ADC virtually eliminates the need for digital error correction, but the analog timing skew minimizing circuits still improve the AC performance.