A Method for Design and Realization of Fast DQPSK

A method for design and realization of fast DQPSK is proposed in this paper for broad band wireless access. Most of the functions of the DQPSK are designed in CPLD. Only the A/D and the Quadratural Multiplier are imolemented in special integrated chips. The frequencies of the carrier at the sending terminal can be adjusted aebitrarily The default is 100250 MHz). The data processing speed can be high up to 10 Mbps, the bit synchronic system of digital dynamic tracing is included, the modulation can be easily altered to 16QAM if needed. The chips can also be rearranged if some other demands are needed in practice. the fast DQPSK designed by our method, therefore, is highly flexible. It can be used in a wide range of applications. 