A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs

A new compact but accurate Verilog-A model for Multi-Level-Cell Phase-change RAMs is proposed in this paper. The previous circuit-based SPICE macromodel has to have a very complicated circuit to describe multi-level resistance thus it needs a long simulation time and occupies large computer memories. This new Verilog-A model can easily model the multi-level resistance by using the partial SET and RESET states where PCRAM resistance changes continuously without having a complicated circuit-based macromodel. Moreover, this new model is more portable, reliable, and simpler than the traditional C-based SPICE model owing to the advantage of Verilog-A. The new model has been compared with the measurement and proved to have good agreement with the measurement.

[1]  Guido Torelli,et al.  A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage , 2009, IEEE Journal of Solid-State Circuits.

[2]  A. Pirovano,et al.  Analysis of phase distribution in phase-change nonvolatile memories , 2004, IEEE Electron Device Letters.

[3]  G.J. Coram,et al.  How to (and how not to) write a compact model in Verilog-A , 2004, Proceedings of the 2004 IEEE International Behavioral Modeling and Simulation Conference, 2004. BMAS 2004..

[4]  Dong Myong Kim,et al.  A compact HSPICE macromodel of resistive RAM , 2007, IEICE Electron. Express.

[5]  A. Pirovano,et al.  A Phase Change Memory Compact Model for Multilevel Applications , 2007, IEEE Electron Device Letters.

[6]  Meng-Hsueh Chiang,et al.  Phase change memory modeling using Verilog-A , 2007, 2007 IEEE International Behavioral Modeling and Simulation Workshop.

[7]  Jin He,et al.  Verilog-A model for phase change memory simulation , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[8]  X.Q. Wei,et al.  HSPICE macromodel of PCRAM for binary and multilevel storage , 2006, IEEE Transactions on Electron Devices.