High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver

This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for different component codewords alternate during the decoding flow. Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles. This inactive period will degrade throughput, especially for small blocks or high parallelism. To resolve this issue, we impose several constraints on the QPP interleaver and rearrange the processing schedule; then the following half-iteration can be executed before the completion of the current half-iteration. Thus, it can eliminate the idle cycles and increase the efficiency of functional units. Based on this modified schedule with 100% efficiency, a parallel turbo decoder which contains 32 radix-24 SISO decoders is implemented with 90 nm technology to achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations.

[1]  Catherine Douillard,et al.  Iterative Decoding of Concatenated Convolutional Codes: Implementation Issues , 2007, Proceedings of the IEEE.

[2]  Joseph R. Cavallaro,et al.  Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards , 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

[3]  Sorin Adrian Barbulescu,et al.  ITERATIVE DECODING OF TURBO CODES AND OTHER CONCATENATED CODES , 1996 .

[4]  An-Yeu Wu,et al.  Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  In-Cheol Park,et al.  A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[6]  Yeheskel Bar-Ness,et al.  A parallel MAP algorithm for low latency turbo decoding , 2002, IEEE Communications Letters.

[7]  Gianluca Piccinini,et al.  Architectural strategies for low-power VLSI turbo decoders , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Ran Ginosar,et al.  Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Claude Berrou,et al.  Organisation de la mémoire dans un turbo décodeur utilisant l'algorithme SUB-MAP , 1999 .

[10]  Ran Ginosar,et al.  Parallel VLSI architecture for MAP turbo decoder , 2002, The 13th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications.

[11]  Cheng-Chi Wong,et al.  A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[12]  S. Dolinar,et al.  Weight distributions for turbo codes using random and nonrandom permutations , 1995 .

[13]  Cheng-Chi Wong,et al.  Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[14]  Michel Jezequel,et al.  Towards an optimal parallel decoding of turbo codes , 2006 .

[15]  John Cocke,et al.  Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.

[16]  Oscar Y. Takeshita,et al.  On maximum contention-free interleavers and permutation polynomials over integer rings , 2005, IEEE Transactions on Information Theory.

[17]  Qiuting Huang,et al.  A 390Mb/s 3.57mm2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[18]  Christian Bettstetter,et al.  Turbo decoding with tail-biting trellises , 1998, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167).

[19]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[20]  Paul Guinand,et al.  Estimating the minimum distance of turbo-codes using double and triple impulse methods , 2005, IEEE Communications Letters.