Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration

Adaptive hardware requires some reconfiguration capabilities. FPGAs with native dynamic partial reconfiguration (DPR) support pose a dilemma for system designers: whether to use native DPR or to build a virtual reconfigurable circuit (VRC) on top of the FPGA which allows selecting alternative functions by a multiplexing scheme. This solution allows much faster reconfiguration, but with higher resource overhead. This paper discusses the advantages of both implementations for a 2D image processing matrix. Results show how higher operating frequency is obtained for the matrix using DPR. However, this is compensated in the VRC during evolution due to the comparatively negligible reconfiguration time. Regarding area, the DPR implementation consumes slightly more resources due to the reconfiguration engine, but adds further more capabilities to the system.

[1]  Marco D. Santambrogio,et al.  A direct bitstream manipulation approach for Virtex4-based evolvable systems , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[2]  Andres Upegui,et al.  Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[3]  Tughrul Arslan,et al.  Evolvable Components—From Theory to Hardware Implementations , 2005, Genetic Programming and Evolvable Machines.

[4]  J. Torresen,et al.  Partial Reconfiguration Applied in an On-line Evolvable Pattern Recognition System , 2008, 2008 NORCHIP.

[5]  Zdenÿek Vaÿ ´ õÿ.  HARDWARE ACCELERATOR OF CARTESIAN GENETIC PROGRAMMING WITH MULTIPLE FITNESS UNITS , 2010 .

[6]  Moritoshi Yasunaga,et al.  An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification , 2007, ICES.

[7]  Jin Wang,et al.  Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware , 2008, IET Comput. Digit. Tech..

[8]  Eduardo de la Torre,et al.  Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support , 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[9]  Eduardo de la Torre,et al.  A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems , 2011, 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).