A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov
暂无分享,去创建一个
[1] Maria J. Avedillo,et al. Multi-threshold threshold logic circuit design using resonant tunnelling devices , 2003 .
[2] V. Gerousis. Design and modeling challenges for 90 NM and 50 NM , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[3] Rahul Sarpeshkar,et al. Analog Versus Digital: Extrapolating from Electronics to Neurobiology , 1998, Neural Computation.
[4] José Pineda de Gyvez,et al. Threshold voltage and power-supply tolerance of CMOS logic design families , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[5] David A. Sprecher,et al. A Numerical Implementation of Kolmogorov's Superpositions II , 1996, Neural Networks.
[6] F. Ellinger,et al. A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.
[7] V. Beiu. The next generation of neural network chips , 1997 .
[8] Konstantin K. Likharev,et al. Electronics Below 10 nm , 2003 .
[9] Valeriu Beiu. 2D Neural Hardware versus 3D Biological Ones , 1998, NC.
[10] Valeriu Beiu,et al. Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL) , 2003, IWANN.
[11] S. Roy,et al. Multiplexing schemes for cost-effective fault-tolerance , 2004, 4th IEEE Conference on Nanotechnology, 2004..
[12] Rüdiger Reischuk,et al. Area Efficient Methods to Increase the Reliability of Circuits , 1992, Data Structures and Efficient Algorithms.
[13] Jie Han,et al. A system architecture solution for unreliable nanoelectronic devices , 2002 .
[14] J. von Neumann,et al. Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .
[15] A. S. Sadek,et al. Fault-tolerant techniques for nanocomputers , 2002 .
[16] U. Ruckert,et al. On nanoelectronic architectural challenges and solutions , 2004, 4th IEEE Conference on Nanotechnology, 2004..
[17] C. Stevens,et al. Changes in reliability of synaptic function as a mechanism for plasticity , 1994, Nature.
[18] Okihiko Ishizuka. Multi-valued multi-threshold networks , 1976 .
[19] Takayasu Sakurai. Low-power and high-speed V VLSI design with low supply voltage through cooperation between levels , 2002, Proceedings International Symposium on Quality Electronic Design.
[20] Justin E. Harlow. Toward design technology in 2020: trends, issues, and challenges [VLSI design] , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..
[21] Pekka Orponen,et al. General-Purpose Computation with Neural Networks: A Survey of Complexity Theoretic Results , 2003, Neural Computation.
[22] 桜井 貴康. [特別招待講演]Prespectives on Power-Aware Electronics : 低電力エレクトロニクスの展望(VSLI一般(ISSCC'03関連特集)) , 2003 .
[23] K. Banerjee,et al. SETMOS: a novel true hybrid SET-CMOS high current Coulomb blockade oscillation cell for future nano-scale analog ICs , 2003, IEEE International Electron Devices Meeting 2003.
[24] R. D. Figueiredo. Implications and applications of Kolmogorov's superposition theorem , 1980 .
[25] Valeriu Beiu,et al. Constructive Threshold Logic Addition A Synopsis of the Last Decade , 2003, ICANN.
[26] Russell Tessier,et al. Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[27] A.P. Chandrakasan,et al. A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[28] Vera Kurková,et al. Kolmogorov's theorem and multilayer neural networks , 1992, Neural Networks.
[29] Yusuf Leblebici,et al. Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..
[30] Donald R. Haring,et al. Multi-threshold threshold elements , 1966, IEEE Trans. Electron. Comput..
[31] Konstantin K. Likharev,et al. Neuromorphic architectures for nanoelectronic circuits , 2004, Int. J. Circuit Theory Appl..
[32] Valeriu Beiu,et al. On Kolmogorov's superpositions and Boolean functions , 1998, Proceedings 5th Brazilian Symposium on Neural Networks (Cat. No.98EX209).
[33] Valeriu Beiu. A survey of perceptron circuit complexity results , 2003, Proceedings of the International Joint Conference on Neural Networks, 2003..
[34] V. Beiu,et al. Optimal neural computations require analog processors , 1998 .
[35] V. Pott,et al. Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive , 2004, IEEE Electron Device Letters.
[36] Avi Mendelson,et al. Coming challenges in microarchitecture and architecture , 2001, Proc. IEEE.
[37] Jeffrey Bokor,et al. Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.
[38] Valeriu Beiu. On automatic synthesis of analog/digital circuits , 1998 .
[39] B. Moyer. Low-power design for embedded processors , 2001 .
[40] Cristian Constantinescu,et al. Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.
[41] Ki-Whan Song,et al. Realistic single-electron transistor modeling and novel CMOS/SET hybrid circuits , 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..
[42] H. Hughes,et al. Radiation effects and hardening of MOS technology: devices and circuits , 2003 .
[43] Ali Keshavarzi,et al. View from the bottom: nanometer technology AC parametric failures - why, where, and how to detect , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.
[44] V. Beiu,et al. Design and analysis of SET circuits: using MATLAB modules and SIMON , 2004, 4th IEEE Conference on Nanotechnology, 2004..
[45] A. S. Sadek,et al. Parallel information and computation with restitution for noise-tolerant nanoscale logic networks , 2003 .
[46] William B Levy,et al. Energy-Efficient Neuronal Computation via Quantal Synaptic Failures , 2002, The Journal of Neuroscience.
[47] Kaushik Roy,et al. Design of low voltage CMOS circuits , 2001, Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573).
[48] Valeriu Beiu,et al. Characterization of a 16-bit threshold logic single-electron technology adder , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[49] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[50] Valeriu Beiu,et al. VLSI implementations of threshold logic-a comprehensive survey , 2003, IEEE Trans. Neural Networks.
[51] Naresh R. Shanbhag,et al. Reliable low-power digital signal processing via reduced precision redundancy , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[52] D. Strukov,et al. CMOL: Devices, Circuits, and Architectures , 2006 .