Moore's law lives on [CMOS transistors]
暂无分享,去创建一个
Jeffrey Bokor | Leland Chang | N. Lindert | Tsu-Jae King | Chenming Hu | J. Kedzierski | Yang-Kyu Choi | Peiqi Xuan | N. Lindert | C. Hu | J. Kedzierski | T. King | J. Bokor | Leland Chang | Yang-Kyu Choi | Peiqi Xuan
[1] D. Frank,et al. Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[2] C. Hu,et al. Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[3] M. Lundstrom,et al. Electron transport in a model Si transistor , 2000 .
[4] S. Horiguchi,et al. ELECTRONIC STRUCTURES AND PHONON-LIMITED ELECTRON MOBILITY OF DOUBLE-GATE SILICON-ON-INSULATOR SI INVERSION LAYERS , 1999 .
[5] Jeffrey Bokor,et al. 60 nm planarized ultra-thin body solid phase epitaxy MOSFETs , 2000, 58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526).
[6] J. Snyder,et al. SUB-40 NM PTSI SCHOTTKY SOURCE/DRAIN METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS , 1999 .
[7] J. Bokor,et al. Quasi-planar NMOS FinFETs with sub-100 nm gate lengths , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).
[8] Chenming Hu,et al. Ultrathin-body SOI MOSFET for deep-sub-tenth micron era , 2000, IEEE Electron Device Letters.
[9] B. Davari. CMOS technology scaling, 0.1 /spl mu/m and beyond , 1996, International Electron Devices Meeting. Technical Digest.
[10] Dimitri A. Antoniadis,et al. Back-gated CMOS on SOIAS for dynamic threshold voltage control , 1997 .
[11] Jeffrey Bokor,et al. 30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D , 2000, 58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526).
[12] Chenming Hu,et al. Ultra-thin body PMOSFETs with selectively deposited Ge source/drain , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).
[13] R.H. Dennard,et al. Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.
[14] Chenming Hu,et al. A folded-channel MOSFET for deep-sub-tenth micron era , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[15] Mehrdad M. Moslehi. Low-temperature in-situ dry cleaning process for epitaxial layer multiprocessing , 1991, Other Conferences.
[16] D. K. Sadana,et al. The Influence Of Ion Implantation On Solid Phase Epitaxy Of Amorphous Silicon Deposited By LPCVD , 1985, Photonics West - Lasers and Applications in Science and Engineering.
[17] J. Bokor,et al. FinFET-a quasi-planar double-gate MOSFET , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[18] Chenming Hu,et al. Threshold voltage shift by quantum confinement in ultra-thin body device , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).
[19] A. Toriumi,et al. Subband structure engineering for performance enhancement of Si MOSFETs , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[20] J. Bokor,et al. Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel , 2000, IEEE Electron Device Letters.
[21] K.P. MacWilliams,et al. Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOS , 1991, IEEE Electron Device Letters.
[22] P. Packan,et al. Pushing the Limits , 1999, Science.
[23] B. Meyerson,et al. Bistable conditions for low‐temperature silicon epitaxy , 1990 .
[24] Chenming Hu,et al. Sub 50-nm FinFET: PMOS , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[25] Philip J. Tobin,et al. Elevated source drain devices using silicon selective epitaxial growth , 2000 .
[26] M. V. Fischetti,et al. Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.
[27] Jeffrey Bokor,et al. Gate length scaling and threshold voltage control of double-gate MOSFETs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).