EPP Based Verification Scheme for Video Chip

Enhanced Parallel Port(EPP) is a simple and reliable means for communication between PC and peripherals.Its reading and writing data protocol is used to implement the EPP_Upload and EPP_Download IP with standard synchronous FIFO-like interface in hardware description language of Verilog.The EPP IPs provide ways for outputing intermediate results and inputing test vectors between FPGA prototype and PC in real-time verification process in ASIC design.The verification of a JPEG2000 encoder chip and digital video decoder chip validates the effectiveness of EPP IP.