Design for Testability—A Survey

This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.

[1]  J. Paul Roth,et al.  A Heuristic Algorithm for the Testing of Asynchronous Circuits , 1971, IEEE Transactions on Computers.

[2]  Gerald M. Masson,et al.  The Boolean Difference and Multiple Fault Analysis , 1975, IEEE Transactions on Computers.

[3]  Thomas M. Storey,et al.  Delay test simulation , 1977, DAC '77.

[4]  James R. Armstrong,et al.  Design of a Graphic Generator for Remote Terminal Application , 1973, IEEE Transactions on Computers.

[5]  Kilin To Fault Folding for Irredundant and Redundant Combinational Circuits , 1973, IEEE Transactions on Computers.

[6]  Edward J. McCluskey,et al.  Design for Autonomous Test , 1981, IEEE Transactions on Computers.

[7]  R. T. Boute,et al.  Optimal and Near-Optimal Checking Experiments for Output Faults in Sequential Machines , 1974, IEEE Transactions on Computers.

[8]  Herbert Y. Chang,et al.  Comparison of Parallel and Deductive Fault Simulation Methods , 1974, IEEE Transactions on Computers.

[9]  F. F. Sellers,et al.  Analyzing Errors with the Boolean Difference , 1968, IEEE Transactions on Computers.

[10]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[11]  Edward J. McCluskey,et al.  Fault Equivalence in Sequential Machines. , 1971 .

[12]  Arthur D. Friedman,et al.  Test Point Placement to Simplify Fault Detection , 1974, IEEE Transactions on Computers.

[13]  Charles R. Kime,et al.  A Module-Level Testing Approach for Combinational Networks , 1976, IEEE Transactions on Computers.

[14]  Jacob Savir,et al.  Syndrome-Testing of " Syndrome-Untestable" Combinational Circuits , 1981, IEEE Transactions on Computers.

[15]  Prabhakar Goel Test generation costs analysis and projections , 1980, DAC '80.

[16]  John P. Hayes,et al.  Detection oF Pattern-Sensitive Faults in Random-Access Memories , 1975, IEEE Transactions on Computers.

[17]  John P. Hayes,et al.  A Nand Model ror Fault Diagnosis in Combinational Logic Networks , 1971, IEEE Transactions on Computers.

[18]  Eugen I. Muehldorf,et al.  LSI logic testing — An overview , 1981, IEEE Transactions on Computers.

[19]  A. K. Susskind Diagnostics for logic networks , 1973, IEEE spectrum.

[20]  H. Ando,et al.  Testing VLSI with Random Access Scan , 1980 .

[21]  John P. Hayes,et al.  Transition Count Testing of Combinational Logic Circuits , 1976, IEEE Transactions on Computers.

[22]  Robert A. Rasmussen,et al.  Delay test generation , 1977, DAC '77.

[23]  Sudhakar M. Reddy,et al.  On Minimally Testable Logic Networks , 1974, IEEE Transactions on Computers.

[24]  John P. Hayes On Modifying Logic Networks to Improve Their Diagnosability , 1974, IEEE Transactions on Computers.

[25]  Francisco J. O. Dias Fault Masking in Combinational Logic Circuits , 1975, IEEE Transactions on Computers.

[26]  Shedletsky,et al.  The Error Latency of a Fault in a Sequential Digital Circuit , 1976, IEEE Transactions on Computers.

[27]  D. C. King Diagnosis and reliable design of digital systems , 1977 .

[28]  B. Koenemann,et al.  Built-in logic block observation techniques , 1979 .

[29]  Predrag G. Kovijanic A new look at test generation and verification , 1977, DAC '77.

[30]  Gernot Metze,et al.  A New Representation for Faults in Combinational Digital Circuits , 1972, IEEE Transactions on Computers.

[31]  Sudhakar M. Reddy,et al.  Fault Detecting Test Sets for Reed-Muller Canonic Networks , 1975, IEEE Transactions on Computers.

[32]  Edward J. McCluskey,et al.  Derivation of optimum test sequences for sequential machines , 1964, SWCT.

[33]  Ernst G. Ulrich,et al.  Fault-test analysis techniques based on logic simulation , 1972, DAC '72.

[34]  L. H. Goldstein,et al.  Controllability/observability analysis of digital circuits , 1978 .

[35]  P. R. Schneider,et al.  On the necessity to examine D-chains in diagnostic test generation-an example , 1967 .

[36]  J. F. Poage,et al.  Derivation of optimum tests to detect faults in combinational circuits , 1962 .

[37]  Douglas B. Armstrong,et al.  On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets , 1966, IEEE Trans. Electron. Comput..

[38]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[39]  Edward J. McCluskey,et al.  Analysis of Logic Circuits with Faults Using Input Signal Probabilities , 1975, IEEE Transactions on Computers.

[40]  Edward B. Eichelberger,et al.  Hazard Detection in Combinational and Sequential Switching Circuits , 1965, IBM J. Res. Dev..

[41]  Sundaram Seshu,et al.  On an Improved Diagnosis Program , 1965, IEEE Trans. Electron. Comput..

[42]  Se June Hong,et al.  Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks , 1971, IEEE Transactions on Computers.

[43]  Stephen A. Szygenda,et al.  A model and implementation of a universal time delay simulator for large digital nets , 1970, AFIPS '70 (Spring).

[44]  Alfred K. Susskind,et al.  Testing by Verifying Walsh Coefficients , 1983, IEEE Transactions on Computers.

[45]  Douglas B. Armstrong,et al.  A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.

[46]  Melvin A. Breuer,et al.  Functional Partitioning and Simulation of Digital Circuits , 1970, IEEE Transactions on Computers.

[47]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[48]  Spiros G. Papaioannou Optimal Test Generation in Combinational Networks by Pseudo-Boolean Programming , 1977, IEEE Transactions on Computers.

[49]  Thomas W. Williams,et al.  Testing Logic Networks and Designing for Testability , 1979, Computer.

[50]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.

[51]  J. Paul Roth,et al.  Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits , 1967, IEEE Trans. Electron. Comput..

[52]  Jacob Savir,et al.  Syndrome-Testable Design of Combinational Circuits , 1980, IEEE Transactions on Computers.

[53]  Stephen S. Yau,et al.  Multiple Fault Detection for Combinational Logic Circuits , 1975, IEEE Transactions on Computers.

[54]  David T. Wang Properties of Faults and Criticalities of Values under Tests for Combinational Networks , 1975, IEEE Transactions on Computers.

[55]  Richard D. Eldred Test Routines Based on Symbolic Logical Statements , 1959, JACM.

[56]  S. DasGupta,et al.  LSI chip design for testability , 1978, 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[57]  Vason P. Srini Fault Location in a Semiconductor Random-Access Memory Unit , 1978, IEEE Transactions on Computers.

[58]  EDWARD J. McCLUSKEY,et al.  Fault Equivalence in Combinational Logic Networks , 1971, IEEE Transactions on Computers.

[59]  Roy C. Ogus,et al.  The Probability of a Correct Output from a Combinational Circuit , 1975, IEEE Transactions on Computers.

[60]  K. C. Y. Mei,et al.  Bridging and Stuck-At Faults , 1974, IEEE Transactions on Computers.

[61]  Peter S. Bottorff,et al.  Automatic checking of logic design structures For compliance with testability ground rules , 1977, DAC '77.

[62]  Ernst G. Ulrich,et al.  Concurrent simulation of nearly identical digital networks , 1974, Computer.

[63]  Jack Edward Stephenson,et al.  A testability measure for register-transfer level digital circuits , 1974 .

[64]  Stephen A. Szygenda,et al.  Modeling and Digital Simulation for Design Verification and Diagnosis , 1976, IEEE Transactions on Computers.

[65]  Rodolfo Betancourt Derivation of Minimum Test Sets for Unate Logical Circuits , 1971, IEEE Transactions on Computers.

[66]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[67]  S. M Reddy,et al.  Easily testable realizations for logic functions , 1973 .

[68]  Attila Tóth,et al.  Automated database-driven digital testing , 1974, Computer.

[69]  Prathima Agrawal,et al.  An Automatic Test Generation System for Illiac IV Logic Boards , 1972, IEEE Transactions on Computers.

[70]  Stephen A. Szygenda TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic , 1972, DAC '72.

[71]  David T. Wang An Algorithm for the Generation of Test Sets for Combinational Logic Networks , 1975, IEEE Transactions on Computers.

[72]  Toshihiro Arima,et al.  Test generation systems in Japan , 1975, DAC '75.

[73]  Frederick C. Hennie,et al.  Finite-state Models for Logical Machines , 1968 .

[74]  Arthur D. Friedman,et al.  Fault detection in digital circuits , 1971 .

[75]  Sundaram Seshu,et al.  The Diagnosis of Asynchronous Sequential Switching Systems , 1962, IRE Trans. Electron. Comput..