A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS
暂无分享,去创建一个
[1] C. Holuigue,et al. A 14b 20mW 640MHz CMOS CT /spl Delta//spl Sigma/ ADC with 20MHz Signal Bandwidth and 12b ENOB , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[2] Venkatesh Srinivasan,et al. A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter , 2010, IEEE Custom Integrated Circuits Conference 2010.
[3] O. Oliaei,et al. Sigma-delta modulator with spectrally shaped feedback , 2003, IEEE Trans. Circuits Syst. II Express Briefs.
[4] Peng Gao,et al. A 2.8-to-8.5mW GSM/bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CTΔΣ with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS , 2010, 2010 Symposium on VLSI Circuits.
[5] Min C. Park,et al. A 0.13µm CMOS 78dB SNDR 87mW 20MHz BW CT ΔΣ ADC with VCO-based integrator and quantizer , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[6] Kofi A. A. Makinwa,et al. A 4GHz CT ΔΣ ADC with 70dB DR and −74dBFS THD in 125MHz BW , 2011, 2011 IEEE International Solid-State Circuits Conference.
[7] Nagendra Krishnapura,et al. Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $\Delta\Sigma$ Modulators , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.