论文信息 - A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method

A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method

This paper presents a 3rd-order continuous time sigma-delta (ΣΔ) modulator (CTSDM) using several low power techniques. A compact architecture of 3rd-order CTSDM is proposed to reduce power dissipation on system level. The loop-filter which is the key block of this CTSDM architecture consists of feedforward p'ath, feedforward amplifier, single-opamp resonator and passive adder. A finite gain bandwidth (GBW) compensation method is used to improve the performance. This modulator is designed with TSMC 65nm CMOS process and archives 80dB SNR in 20MHz signal bandwidth while the FOM is 35fJ/conv.

Junyan Ren | Jingjing Wang | Jun Xu | Chixiao Chen | Zemin Feng

[1] Koji Obata,et al. A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver , 2010, IEEE Custom Integrated Circuits Conference 2010.

[2] Junyan Ren,et al. A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator , 2013, 2013 IEEE 10th International Conference on ASIC.

[3] Koji Obata,et al. A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[4] W. Sansen,et al. Transconductance with capacitances feedback compensation for multistage amplifiers , 2004, IEEE Journal of Solid-State Circuits.

[5] Ping Chen,et al. A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.