Autonomous Event Driven Model of Second Order Voltage Switched Charge Pump PLL

The charge-pump Phase-Locked Loop (CP-PLL) is a widely used subsystem in wireless communication and smart system applications to perform the function of frequency synthesizer. Since the CP-PLL is a mixed-signal system, it is more complex to analyze the system behavior, especially when a voltage switched charge-pump-PLL (VSCP-PLL) is used. A more robust approach is required for such a non-linear pulse width modulated system, where the overall gain of the loop is varying due to non-constant pump current. To analyze the sampled behavior of a VSCP-PLL, the Event Driven (ED) model based on discrete-time phase equations is one of the powerful and resource efficient tool. In this brief, an autonomous ED model (time-independent and linear to fixed point) is developed for a second order VSCP-PLL by modifying the ED approach. The developed Autonomous ED-model is validated using the ED simulations in the locked state.

[1]  Rafael Castro-Lopez,et al.  Analog/RF and Mixed-Signal Circuit Systematic Design , 2013 .

[2]  S.C. Gupta,et al.  Phase-locked loops , 1975, Proceedings of the IEEE.

[3]  Salvatore Levantino,et al.  Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Liming Xiu Clock Technology: The Next Frontier , 2017, IEEE Circuits and Systems Magazine.

[5]  Mark Van Paemel,et al.  Analysis of a charge-pump PLL: a new model , 1994, IEEE Trans. Commun..

[6]  Melanie Hartmann,et al.  Design Of Analog Cmos Integrated Circuits , 2016 .

[7]  Wenceslas Rahajandraibe,et al.  Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  V. Petridis,et al.  Voltage Pump Phase-Locked Loops , 1985, IEEE Transactions on Industrial Electronics.

[9]  Ulrich Hilleringmann,et al.  Stability Analysis of a Charge Pump Phase-Locked Loop Using Autonomous Difference Equations , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Woo-Young Choi,et al.  A 0.4-V, 90 $\sim$ 350-MHz PLL With an Active Loop-Filter Charge Pump , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[12]  Shin-Il Lim,et al.  Charge pump with perfect current matching characteristics in phase-locked loops , 2000 .