Parade: power analysis resistive architecture design

With wide adoption of embedded systems, the security aspect of embedded systems is becoming significantly important. Especially, power analysis side-channel attack, which is a type of attack on embedded hardware encryption/decryption systems, is a substantive security threat. Since power information has a correlation with the sensitive data that have to be protected from adversaries, the power consumption data become the ''side-channel'' of crypto-hardware. Power analysis side-channel attacks find such a correlation from collected many power consumption sample data. Countermeasures against the power analysis side-channel attacks are available; however, conventional countermeasures incur area, power, and performance overheads. Furthermore, hardware designers need to make trade-off decisions between the countermeasure resistivity and those overheads. This thesis proposes PARADE (Power Analysis Resistive Architecture DEsign) techniques to overcome such difficulties in designing secure embedded systems against power analysis side-channel attacks. In particular, the proposed method reduces the risk of power analysis side-channel attacks and the overhead of countermeasure by covering three key approaches of countermeasures: randomization, balancing, time-shifting. The first contribution in PARADE techniques is ExCCel (Exploration of Complementary Cells) that helps generating randomizing hardware countermeasure. ExCCel automates selective insertion of complementary cells that simultaneously improves attack resistivity while lowering the area and energy overheads in a simulated annealing manner. The second contribution, HDRL (Homogeneous Dual-Rail Logic), provides a power balancing technique. HDRL theoretically guarantees fully balanced power consumption using only standard cells and significantly improves power analysis side-channel attack resistivity. The third contribution, LRCG (Latch-based Random Clock-Gating), achieves realization of the time-shifting hardware in ASIC design. LRCG casts the problem of power analysis attacks as a retiming problem of circuits and automate latch-based circuit design process. Latch-based circuit, retiming, and clock-gating are traditionally used for performance and low power design, however LRCG randomly change the clock timing (time-shifting) using clock-gating techniques on latch-based circuit to obfuscate the power signature of crypto-hardware. Accordingly, the PARADE covers the three key directions of countermeasures. This thesis theoretically and experimentally demonstrates that the proposed PARADE techniques reduce the area, energy, performance overheads as well as enhancing the power analysis resistivity. The advantages of low overheads and better resistivity makes the proposed contributions promising approaches for designing smart cards and mobile devices.