A Scheme For Integrated Controller-datapath Fault Testing

In systems consisting of interacting datapaths and controllers and utilizing built-in self test (BIST), the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This work facilitates the testing of datapath-controller pairs in an integrated fashion. The key to the approach is the addition of logic to the system that interacts with the existing controller to push the effects of controller faults i n t o the data pow, so that they can be observed at the datapath registers rather than directly a t the controller outputs. The result is to reduce the BIST overhead over what is needed if the datapath and controller are tested independently, and to allow a more complete test of the interface between datapath and controller. Fault coverage and overhead results are given for four example circuits.

[1]  Melvin A. Breuer,et al.  Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[2]  Melvin A. Breuer,et al.  Test Schedules for VLSI Circuits Having Built-In Test Hardware , 1986, IEEE Transactions on Computers.

[3]  F. Fummi,et al.  Synthesis for testability of large complexity controllers , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[4]  Hans-Joachim Wunderlich,et al.  Optimized synthesis of self-testable finite state machines , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

[5]  David E. Long,et al.  Increasing testability by clock transformation (getting rid of those darn states) , 1996, Proceedings of 14th VLSI Test Symposium.