Interconnect Modeling and Design With Consideration of Inductance

Given the growing importance of interconnects in performance, reliability, cost, and power dissipation for high-performance circuits and systems, interconnect modeling and optimization has been an active research area [1]. However, most existing work on interconnect modeling and optimization assumes an RC interconnect model, which becomes increasingly inadequate as the on-chip inductive effect gains prominence in gigahertz designs. A simple rule of thumb is that the inductance should be considered if resistance R and reactance ωL have similar values, where L is inductance and ω = 2πf with f being the operating frequency. In Figure 1(a), we compare R and ωL under different operating frequencies. We used the three-dimensional electromagnetic field solver Fast Henry [2] to compute R and ωL for a typical global interconnect, which is 0.8µm wide, 2µm tall, and 2000µm long. One may easily see that ωL starts to outweigh the resistance at the operating frequency of approximate one gigahertz. As the operating frequency is larger than the clock frequency due to the harmonic effect,1 on-chip inductance should be considered in the layout design for circuits of gigahertz clock frequencies.