Lithographic Performance and Mix-and-Match Lithography Using 100 kV Electron Beam System JBX-9300 FS

Recently, for the increase in the performance of logic devices, the feature size of CMOS devices is rapidly decreasing less than 100 nm as predicted by ITRS 1999 (International Technology Roadmap for Semiconductors). [1] Lithography technology is the key to realize sub-100-nm high-performance devices, then several types of high-throughput lithography tools are under development such as F2 excimer laser lithography, EUV (Extremely Ultra Violet) lithography and EPL (Electron Projection Lithography). On the other hand, advanced CMOS devices with a gate length of less than 100 nm should be also developed ahead of mass production. For this purpose, high-resolution point electron beam lithography is only a tool for the research and development of devices on a full wafer. We have introduced an advanced point electron beam system, JBX-9300FS, which is designed for the development of advanced devices with a small feature size on a large silicon wafer. In this report, the performance of JBX-9300FS on lithography and development of Mix-and-Match lithography are described.