A cell-replicating approach to minicut-based circuit partitioning

An extension to the Fiduccia and Mattheyses minicut algorithm (1982) allows cells to be replicated in both sides of the partition. This technique can substantially reduce the number of cut nets in a partitioned network below what can be obtained without replication. The extensions to the algorithm to permit replication are easily implemented and maintain the linear-time complexity of the algorithm. This technique is dependent solely upon the interconnect topology and the direction of signal flows between cells and nets. The formulation of cell gains is extended to model the effect of cell replication, and the necessary modifications to the algorithm are described.<<ETX>>

[1]  F. Hwang.  On Steiner Minimal Trees with Rectilinear Distance , 1976 .

[2]  Srinivas Devadas,et al.  On the verification of sequential machines at differing levels of abstraction , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Michael Burstein,et al.  Hierarchical Channel Router , 1983, 20th Design Automation Conference Proceedings.

[4]  Wu-Tung Cheng,et al.  Differential Fault Simulation - A Fast Method Using Minimal Memory , 1989, 26th ACM/IEEE Design Automation Conference.

[5]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[6]  Michael D. Ciletti,et al.  Arrangement of latches in scan-path design to improve delay fault coverage , 1990, Proceedings. International Test Conference 1990.

[7]  Alberto L. Sangiovanni-Vincentelli,et al.  Logic Verification Algorithms and their Parallel Implementation , 1987, 24th ACM/IEEE Design Automation Conference.

[8]  A. Richard Newton,et al.  Don't care minimization of multi-level sequential logic networks , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[9]  Masahiro Fujita,et al.  On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..

[10]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[11]  Sungju Park,et al.  Why is less information from logic simulation more useful in fault simulation? , 1990, Proceedings. International Test Conference 1990.

[12]  Ahsan Abdullah,et al.  Topological via minimization and routing , 1991, [1991] Proceedings. First Great Lakes Symposium on VLSI.

[13]  Magdy Abadir,et al.  A Knowledge-Based System for Designing Testable VLSI Chips , 1985, IEEE Design & Test of Computers.

[14]  Kai Hwang,et al.  Computer architecture and parallel processing , 1984, McGraw-Hill Series in computer organization and architecture.

[15]  Ernst G. Ulrich,et al.  Concurrent simulation of nearly identical digital networks , 1973, Computer.

[16]  Shimon Even,et al.  Graph Algorithms , 1979 .

[17]  Daniel Gajski,et al.  LES: a layout expert system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Richard M. Karp,et al.  Minimization Over Boolean Graphs , 1962, IBM J. Res. Dev..

[19]  Alberto Sangiovanni-Vincentelli,et al.  Logic synthesis for vlsi design , 1989 .

[20]  Uehara,et al.  Optimal Layout of CMOS Functional Arrays , 1981 .

[21]  Pravin M. Vaidya,et al.  A new algorithm for minimizing convex functions over convex sets , 1989, 30th Annual Symposium on Foundations of Computer Science.

[22]  Douglas B. Armstrong,et al.  A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.

[23]  Sudhakar M. Reddy,et al.  On Testable Design for CMOS Logic Circuits , 1983, International Test Conference.

[24]  Yang Cai,et al.  Minimizing channel density by shifting blocks and terminals , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[25]  Bill Underwood,et al.  The parallel-test-detect fault simulation algorithm , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[26]  Jonathan Rose,et al.  Chortle: a technology mapping program for lookup table-based field programmable gate arrays , 1990, 27th ACM/IEEE Design Automation Conference.

[27]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[28]  Takeshi Yoshimura,et al.  New placement and global routing algorithms for standard cell layouts , 1991, DAC '90.

[29]  Zvonko G. Vranesic,et al.  On Fault Detection in CMOS Logic Networks , 1983, 20th Design Automation Conference Proceedings.

[30]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  Roy L. Russo,et al.  A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs , 1971, IEEE Transactions on Computers.

[32]  Robert K. Brayton,et al.  Timing optimization of combinational logic , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[33]  T. Ohtsuki,et al.  Recent advances in VLSI layout , 1990, Proc. IEEE.

[34]  Robert K. Brayton,et al.  The use of observability and external don't cares for the simplification of multi-level networks , 1991, DAC '90.

[35]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[36]  Ernest S. Kuh,et al.  Glitter: A Gridless Variable-Width Channel Router , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[37]  Robert K. Brayton,et al.  Multi-Level Logic Simplification Using Don't Cares and Filters , 1989, 26th ACM/IEEE Design Automation Conference.

[38]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[39]  Kurt Keutzer.  DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.

[40]  Ronald L. Rivest,et al.  A "Greedy" Channel Router , 1982, DAC 1982.

[41]  Gary D. Hachtel,et al.  Performance enhancements in BOLD using 'implications' , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[42]  Robert K. Brayton,et al.  Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[43]  Kewal K. Saluja,et al.  Fast test generation for sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[44]  Yang Cai,et al.  Optimal channel pin assignment , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[45]  I. Cederbaum,et al.  Optimal backboard ordering through the shortest path algorithm , 1974 .

[46]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[47]  Joseph L. A. Hughes.  Multiple fault detection using single fault test sets , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[48]  Yashwant K. Malaiya,et al.  Modeling and Testing for Timing Faults in Synchronous Sequential Circuits , 1984, IEEE Design & Test of Computers.

[49]  Robert E. Tarjan,et al.  Depth-First Search and Linear Graph Algorithms , 1972, SIAM J. Comput..

[50]  Sudhakar M. Reddy,et al.  On the design of robust testable CMOS combinational logic circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[51]  Takeshi Yoshimura,et al.  Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[52]  Kenneth J. Supowit,et al.  Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1990, IEEE Trans. Computers.

[53]  Helmut Simonis,et al.  Test Generation using the Constraint Logic Programming Language CHIP , 1989, International Conference on Logic Programming.

[54]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[55]  Robert K. Brayton,et al.  Logic synthesis for programmable gate arrays , 1991, DAC '90.

[56]  Wentai Liu,et al.  Unconstrained via minimization for topological multilayer routing , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[57]  Takashi Satoh,et al.  A high packing density module generator for CMOS logic cells , 1988, DAC '88.

[58]  Dana S. Richards,et al.  An optimal Steiner tree algorithm for a net whose terminals lie on the perimeter of a rectangle , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[59]  Balakrishnan Krishnamurthy,et al.  An Improved Min-Cut Algonthm for Partitioning VLSI Networks , 1984, IEEE Transactions on Computers.

[60]  Kwang-Ting Cheng,et al.  Functional test generation for finite state machines , 1990, Proceedings. International Test Conference 1990.

[61]  D. T. Lee,et al.  Rectilinear shortest paths in the presence of rectangular barriers , 1989, Discret. Comput. Geom..

[62]  Masahiro Fujita,et al.  Evaluation and improvement of Boolean comparison method based on binary decision diagrams , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[63]  Alberto L. Sangiovanni-Vincentelli,et al.  A New Symbolic Channel Router: YACR2 , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[64]  P. Groeneveld,et al.  On Global Wire Ordering for Macro-Cell Routing , 1989, 26th ACM/IEEE Design Automation Conference.

[65]  Yashwant K. Malaiya,et al.  A New Fault Model and Testing Technique for CMOS Devices , 1982, International Test Conference.

[66]  Srinivas Devadas,et al.  Sequential test generation at the register-transfer and logic levels , 1991, DAC '90.

[67]  Prathima Agrawal,et al.  CONTEST: a concurrent test generator for sequential circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[68]  Srinivas Devadas,et al.  Heuristic minimization of Boolean relations using testing techniques , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[69]  Sungho Kang,et al.  Linear Ordering and Application to Placement , 1983, 20th Design Automation Conference Proceedings.

[70]  John Paul Shen,et al.  Extraction and simulation of realistic CMOS faults using inductive fault analysis , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[71]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[72]  Sudhakar M. Reddy,et al.  Transistor Level Test Generation for MOS Circuits , 1985, DAC 1985.

[73]  M. Hanan,et al.  On Steiner’s Problem with Rectilinear Distance , 1966 .

[74]  石浦 菜岐佐,et al.  A Class of Logic Functions Expressible by a Polynomial-Size Binary Decision Diagram , 1989 .

[75]  Ulrich Lauther,et al.  A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation , 1979, 16th Design Automation Conference.

[76]  Erik Meineche Schmidt,et al.  The Complexity of Equivalence and Containment for Free Single Variable Program Schemes , 1978, ICALP.

[77]  Toshinobu Kashiwabara,et al.  Exact algorithms for multilayer topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[78]  Gary D. Hachtel,et al.  New ATPG techniques for logic optimization , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[79]  Giovanni De Micheli,et al.  Technology mapping for a two-output RAM-based field programmable gate array , 1991, Proceedings of the European Conference on Design Automation..

[80]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .

[81]  Parimal Pal Chaudhuri,et al.  Design of Testable VLSI Circuits with Minumum Area Overhead , 1989, IEEE Trans. Computers.

[82]  Jacob A. Abraham,et al.  MURPHY: A LOGIC SIMULATOR FOR MOS VLSI CIRCUITS. , 1983 .

[83]  Randal E. Bryant,et al.  Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation , 1989, 26th ACM/IEEE Design Automation Conference.

[84]  Ron Y. Pinter,et al.  Optimal Routing in Rectilinear Channels , 1981 .

[85]  Moazzem Hossain,et al.  On topological via minimization and routing , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[86]  Barry K. Rosen,et al.  HSS--A High-Speed Simulator , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[87]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[88]  J. Paul Roth,et al.  Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits , 1967, IEEE Trans. Electron. Comput..

[89]  Melvin A. Breuer,et al.  A systematic approach for designing testable VLSI circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[90]  Bernd Becker,et al.  Structure based methods for parallel pattern fault simulation in combinational circuits , 1991, Proceedings of the European Conference on Design Automation..

[91]  Ron Y. Pinter,et al.  On minimizing channel density by lateral shifting , 1983 .

[92]  Gary D. Hachtel,et al.  BOLD: The Boulder Optimal Logic Design system , 1989, [1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track.

[93]  W.-T. Cheng,et al.  The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[94]  Dwight D. Hill,et al.  Experiments using automatic physical design techniques for optimizing circuit performance , 1989, Proceedings of the 32nd Midwest Symposium on Circuits and Systems,.

[95]  John P. Hayes,et al.  Layout optimization of static CMOS functional cells , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[96]  Kewal K. Saluja,et al.  Test Scheduling and Control for VLSI Built-In Self-Test , 1988, IEEE Trans. Computers.

[97]  Robert K. Brayton,et al.  An exact minimizer for Boolean relations , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[98]  Michael H. Schulz,et al.  Hierarchical test pattern generation based on high-level primitives , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[99]  Kellogg S. Booth,et al.  Testing for the Consecutive Ones Property, Interval Graphs, and Graph Planarity Using PQ-Tree Algorithms , 1976, J. Comput. Syst. Sci..

[100]  M. Ray Mercer,et al.  A method of delay fault test generation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[101]  David S. Johnson,et al.  The Rectilinear Steiner Tree Problem is NP Complete , 1977, SIAM Journal of Applied Mathematics.

[102]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[103]  Alberto Sangiovanni-Vincentelli,et al.  Optimization-based transistor sizing , 1988 .

[104]  Massoud Pedram,et al.  Layout driven technology mapping , 1991, 28th ACM/IEEE Design Automation Conference.

[105]  Majid Sarrafzadeh,et al.  An optimal algorithm for the maximum two-chain problem , 1990, SODA '90.

[106]  Chak-Kuen Wong,et al.  Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[107]  Ernest S. Kuh,et al.  An Algorithm for Performance-Driven Placement of Cell-Based ICs , 1991 .

[108]  Kjell O. Jeppson,et al.  CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[109]  Philip E. Gill,et al.  Practical optimization , 1981 .

[110]  Ron Y. Pinter,et al.  Optimal Chaining of CMOS Transistors in a Functional Cell , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[111]  Knut M. Just,et al.  PALACE: a layout generator for SCVS logic blocks , 1991, DAC '90.

[112]  Prabhakar Goel.  Test generation costs analysis and projections , 1980, DAC '80.

[113]  Majid Sarrafzadeh,et al.  A new approach to topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[114]  Tetsuo Asano,et al.  Routing Region Definition and Ordering Scheme for Building-Block Layout , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[115]  Rajeev Murgai,et al.  Improved logic synthesis algorithms for table look up architectures , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[116]  J. Gillis,et al.  Matrix Iterative Analysis , 1961 .

[117]  S. Davidson,et al.  Sequential Circuit Test Generator (STG) benchmark results , 1989, IEEE International Symposium on Circuits and Systems,.

[118]  Giovanni De Micheli,et al.  Observability don't care sets and Boolean relations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[119]  Wojciech Maly,et al.  Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.

[120]  Nagisa Ishiura,et al.  Shared binary decision diagram with attributed edges for efficient Boolean function manipulation , 1990, 27th ACM/IEEE Design Automation Conference.

[121]  Janusz Rajski,et al.  A method of fault analysis for test generation and fault diagnosis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[122]  Tohru Kikuno,et al.  A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[123]  Dan Trietsch.  Interconnecting networks in the plane: The steiner case , 1990, Networks.

[124]  Robert K. Brayton,et al.  Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[125]  Vishwani D. Agrawal,et al.  Test function specification in synthesis , 1991, DAC '90.

[126]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[127]  N. S. Mendelsohn,et al.  Two Algorithms for Bipartite Graphs , 1963 .

[128]  J. Hartmanis,et al.  Algebraic Structure Theory Of Sequential Machines , 1966 .

[129]  Gary D. Hachtel,et al.  Verification algorithms for VLSI synthesis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[130]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[131]  Donald S. Fussell,et al.  Topological channel routing [VLSI] , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[132]  Edward J. McCluskey,et al.  The critical path for multiple faults , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[133]  Takuji Ogihara,et al.  Test generation for sequential circuits using individual initial value propagation , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[134]  Masahiro Fujita,et al.  Boolean resubstitution with permissible functions and binary decision diagrams , 1991, DAC '90.

[135]  Premachandran R. Menon,et al.  Symbolic test generation for hierarchically modeled digital systems , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[136]  Jonathan Rose,et al.  Chortle-crf: fast technology mapping for lookup table-based FPGAs , 1991, 28th ACM/IEEE Design Automation Conference.

[137]  Dwight D. Hill,et al.  Benchmarks for cell synthesis , 1991, DAC '90.

[138]  Janak H. Patel,et al.  PROOFS: a super fast fault simulator for sequential circuits , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[139]  E. Kuh,et al.  One-dimensional logic gate assignment and interval graphs , 1979, COMPSAC.

[140]  Pankaj K. Agarwal,et al.  Algorithms for special cases of rectilinear steiner trees: I. Points on the boundary of a rectilinear rectangle , 1990, Networks.

[141]  Robert K. Brayton,et al.  Observability relations and observability don't cares , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[142]  Joseph JáJá,et al.  On routing two-terminal nets in the presence of obstacles , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[143]  John A. Waicukauski,et al.  Transition Fault Simulation by Parallel Pattern Single Fault Propagation , 1986, International Test Conference.

[144]  Robert K. Brayton,et al.  Performance-oriented technology mapping , 1990 .

[145]  David N. Deutsch.  A “DOGLEG” channel router , 1976, DAC 1976.

[146]  Takeshi Yoshimura.  An Efficient Channel Router , 1984, 21st Design Automation Conference Proceedings.

[147]  Gene H. Golub,et al.  Matrix computations , 1983 .

[148]  Shuo Huang,et al.  Improved gate matrix layout , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[149]  Janak H. Patel,et al.  An architectural level test generator for a hierarchical design environment , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.

[150]  J. Ecker.  Geometric Programming: Methods, Computations and Applications , 1980 .

[151]  Chak-Kuen Wong,et al.  Optimal Wiring of Movable Terminals , 1983, IEEE Transactions on Computers.

[152]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[153]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[154]  Konrad Doll,et al.  Analytical placement: a linear or a quadratic objective function? , 1991, 28th ACM/IEEE Design Automation Conference.

[155]  Alfred V. Aho,et al.  Rectilinear steiner trees: Efficient special-case algorithms , 1977, Networks.

[156]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[157]  Jason Cong,et al.  On the k-layer planar subset and via minimization problems , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[158]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[159]  Eduard Cerny,et al.  An Approach to Unified Methodology of Combinational Switching Circuits , 1977, IEEE Transactions on Computers.

[160]  Randal E. Bryant,et al.  Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator , 1985, DAC 1985.

[161]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[162]  Janak H. Patel,et al.  PROOFS: a fast, memory efficient sequential circuit fault simulator , 1990, 27th ACM/IEEE Design Automation Conference.

[163]  Don E. Ross,et al.  Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams , 1991, 28th ACM/IEEE Design Automation Conference.

[164]  KENNETH J. SUPOWIT,et al.  Finding a Maximum Planar Subset of a Set of Nets in a Channel , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[165]  Thomas G. Szymanski.  Dogleg Channel Routing is NP-Complete , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[166]  Frederick J. Hill,et al.  Introduction to Switching Theory and Logical Design , 1968 .

[167]  Donald G. Baltus,et al.  SOLO: a generator of efficient layouts from optimized MOS circuit schematics , 1988, DAC '88.

[168]  Albert R. Wang,et al.  Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[169]  Reuven Bar-Yehuda,et al.  Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[170]  Robert K. Brayton,et al.  Extracting local don't cares for network optimization , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[171]  Ibrahim N. Hajj.  An algebra for switch-level simulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[172]  Irith Pomeranz,et al.  On achieving a complete fault coverage for sequential machines using the transition fault model , 1991, 28th ACM/IEEE Design Automation Conference.

[173]  Wolfram Büttner,et al.  Embedding Boolean Expressions into Logic Programming , 1987, J. Symb. Comput..

[174]  Srinivas Devadas,et al.  Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[175]  Seh-Woong Jeong,et al.  ATPG aspects of FSM verification , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[176]  Tobias Nipkow,et al.  Boolean Unification - The Story So Far , 1989, J. Symb. Comput..

[177]  Randal E. Bryant,et al.  COSMOS: a compiled simulator for MOS circuits , 1987, DAC '87.

[178]  Chi W. Yau,et al.  An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[179]  S. Sahni,et al.  Optional linear arrangement of circuit components , 1987 .

[180]  Paul Glick,et al.  An Over-The-Cell Router , 1980, 17th Design Automation Conference.

[181]  Robert K. Brayton,et al.  SLIP: a software environment for system level interactive partitioning , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[182]  Wojciech Maly,et al.  Test generation for current testing , 1989, [1989] Proceedings of the 1st European Test Conference.

[183]  Sudhakar M. Reddy,et al.  Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits , 1986, IEEE Transactions on Computers.

[184]  Akihiro Hashimoto,et al.  Wire routing by optimizing channel assignment within large apertures , 1971, DAC.

[185]  Georg Sigl,et al.  GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[186]  John P. Hayes,et al.  Hierarchical test generation using precomputed testsd for modules , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[187]  Wojciech Maly,et al.  Testing oriented analysis of CMOS ICs with opens , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[188]  Constantin Halatsis,et al.  Irredundant Normal Forms and Minimal Dependence Sets of a Boolean Function , 1978, IEEE Transactions on Computers.

[189]  Srinivas Devadas,et al.  Topological Optimization of Multiple-Level Array Logic , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[190]  Tamotsu Kasai,et al.  A hierarchical algorithm for one-dimensional gate assignment based on contraction of nets , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[191]  Sundaram Seshu,et al.  On an Improved Diagnosis Program , 1965, IEEE Trans. Electron. Comput..