A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip

This paper presents a deadlock-free fault-tolerant routing algorithm for irregular mesh network-on-chips based on a region-based approach. In this approach, a set of rectangular faulty regions called faulty blocks is formed for faulty nodes and a detour path is defined for each faulty block to indicate how packets must detour thefaulty block. The most recent routing algorithm on this approach is Message-Route (Holsmark and Kumar J Inf Sci Eng 23:1649–1662, 2007) which does not have restrictions on the number of tolerable faulty nodes and its distribution. However, this algorithm has three crucial problems; (1) this algorithm fails to provide complete and deadlock-free routing, (2) many nonfaulty nodes are contained in faulty blocks and thus deactivated, and (3) complex routing functions are not feasible for hardware implementation. In this paper, we give a solution for each of the above three problems. We correct the errors of Message-Route to make it complete and deadlock-free. Then, we propose a deadlock-free fault-tolerant routing algorithm which can work under small-sized faulty blocks with a simple routing control. Experimental results show that the proposed algorithm significantly reduces the size of faulty blocks and improves communication latency for both random and cluster faults. Moreover, an FPGA implementation of the proposed algorithm is also discussed.

[1]  Sun-Yuan Kung,et al.  Fault-Tolerant Array Processors Using Single-Track Switches , 1989, IEEE Trans. Computers.

[2]  Shashi Kumar,et al.  Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks , 2007, J. Inf. Sci. Eng..

[3]  Shashi Kumar,et al.  Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions , 2008, J. Syst. Archit..

[4]  Lionel M. Ni,et al.  Fault-tolerant routing in hypercube multicomputers using local safety information , 1996 .

[5]  Lionel M. Ni,et al.  The turn model for adaptive routing , 1992, ISCA '92.

[6]  José Duato,et al.  A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks , 1993, IEEE Trans. Parallel Distributed Syst..

[7]  L. Benini,et al.  Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.

[8]  Axel Jantsch,et al.  Interconnect-Centric Design for Advanced SOC and NOC , 2010 .

[9]  Ge-Ming Chiu,et al.  Fault-Tolerant Routing Algorithm for Meshes without Using Virtual Channels , 1998, J. Inf. Sci. Eng..

[10]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[11]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[12]  Jie Wu,et al.  A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model , 2003, IEEE Trans. Computers.