A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8/spl times/ to 10/spl times/ of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in the proposed design such that the power dissipation as well as the active area is drastically reduced. The design is carried out by TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the voltage-controlled delay tap line at the midway of the working range. Meanwhile, the power dissipation is 52.5 mW at 1.2 GHz output.

[1]  Yiu-Fai Chan,et al.  A portable digital DLL for high-speed CMOS interface circuits , 1999, IEEE J. Solid State Circuits.

[2]  P. R. Gray,et al.  A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000 .

[3]  Beomsup Kim,et al.  PLL/DLL system noise analysis for low jitter clock synthesizer design , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[4]  Naresh R. Shanbhag,et al.  Information-theoretic bounds on average signal transition activity [VLSI systems] , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Dietmar Müller,et al.  Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses , 2000, PATMOS.

[6]  Jae-Kyung Wee,et al.  A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM , 2002, IEEE J. Solid State Circuits.

[7]  George Varghese,et al.  Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Jacques C. Rudell,et al.  A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications , 1997, IEEE J. Solid State Circuits.

[9]  Shishpal Rawat,et al.  EDA challenges facing future microprocessor design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Ho-Jin Park,et al.  A DLL based 10-320 MHz clock synchronizer , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[11]  Sung Dae Lee,et al.  A high speed and low power phase-frequency detector and charge-pump , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[12]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[13]  Shen-Iuan Liu,et al.  A wide-range delay-locked loop with a fixed latency of one clock cycle , 2002, IEEE J. Solid State Circuits.

[14]  Qiuting Huang,et al.  A glitch-free single-phase CMOS DFF for gigahertz applications , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[15]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[16]  Paul R. Gray,et al.  Frequency Multiplier Technique for PCS Applications , 2000 .

[17]  Luca Benini,et al.  Architectures and synthesis algorithms for power-efficient businterfaces , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..