A novel and efficient timing-driven global router for standard cell layout design based on critical network concept

This paper presents a novel timing-driven global routing algorithm for standard cell (SC) layout design based on a critical network concept. The essence of this algorithm is different from that of the typical existing methods, such as the nets-based method and the critical-path-based method. The timing optimization strategy presented in this algorithm is more optimal than the typical existing ones, which makes it possible to reduce the delay in an overall survey. This algorithm has been implemented and tested by MCNC benchmark circuits in this paper. We compared the experimental results between our algorithm and the existing ones. The experimental results show that this algorithm is able to control the delay of the circuit efficiently, and causes little negative effect on other optimizing objectives.

[1]  J. Cong,et al.  Interconnect design for deep submicron ICs , 1997, ICCAD 1997.

[2]  Jason Cong,et al.  Optimal wiresizing for interconnects with multiple sources , 1995, ICCAD.

[3]  N. Nettleton,et al.  Dense, performance directed, auto place and route , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[4]  D. F. Wong,et al.  Optimal wire-sizing formula under the Elmore delay model , 1996, 33rd Design Automation Conference Proceedings, 1996.

[5]  Xianlong Hong,et al.  TIGER: an efficient timing-driven global router for gate array and standard cell layout design , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Chung-Kuan Cheng,et al.  Timing optimization for multisource nets , 1999 .

[7]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[8]  T. Sakurai,et al.  Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.

[9]  Bao Hai A Novel Random Global Routing Algorithm Independent of Net Ordering , 2001 .

[10]  Xianlong Hong,et al.  An Efficient Timing-Driven Global Routing Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[11]  Jason Cong,et al.  Optimal wiresizing under Elmore delay model , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Jun Gu,et al.  An efficient congestion optimization algorithm for global routing based on search space traversing technology , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[13]  Andrew B. Kahng,et al.  International Symposium on Physical Design (ISPD) , 2002, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Vishwani D. Agrawal,et al.  Chip Layout Optimization Using Critical Path Weighting , 1984, 21st Design Automation Conference Proceedings.

[15]  Xianlong Hong,et al.  Performance-Driven Steiner Tree Algorithms for Global Routing , 1993, 30th ACM/IEEE Design Automation Conference.

[16]  Yasuyuki Fujihara,et al.  DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions , 1989, 26th ACM/IEEE Design Automation Conference.

[17]  Liang Yin,et al.  An efficient analytical model of coupled on-chip RLC interconnects , 2001, ASP-DAC '01.

[18]  Sachin S. Sapatnekar,et al.  A timing-constrained algorithm for simultaneous global routing of multiple nets , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[19]  Martin D. F. Wong,et al.  An efficient and optimal algorithm for simultaneous buffer and wire sizing , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..