Convenient method of digital PI-CDR lock-detection for phase noise elimination and enhanced jitter tolerance

A lock-detector for the digital phase interpolator based clock and dada recovery circuit (PI-CDR) is proposed. The simple method could commendably lock the PI-control code when the CDR is locked, which eliminates the systematic phase noise of the recovered clock without reducing the jitter tolerance ability. The proposed architecture is implemented in 0.13 μm CMOS and occupies area of 0.18 mm2.