A high-density and quick-turnaround macrocell design method for custom VLSIs is applied to a 500 k-transistor protocol control chip, resulting in a density of about 4000 transistors/mm/sup 2/ using 0.8- mu m BiCMOS technology. An automated adaptive macrocell and a short-time custom VLSI design methodology were developed to make the logic and physical design more adaptable by offering greater variety of bit width, word length, circuit type, and signal terminals. The adaptive macrocell generation procedure consists of a logical description and a physical description with minimum information on the composition of complete macrocells, suitable for all specific uses. The variables providing adaptability are parameterized in this procedure, which is hierarchically described by network information among leaf cells or submacrocells, together with their topological placement information, permitting the adaptive macrocell to be generated automatically. An example of an ALU (arithmetic logic unit) circuit generated as a data-path submacrocell is shown. To verify the effectiveness of the proposed method, various kinds of macrocells were generated and fabricated using the 0.8- mu m, double-metal BiCMOS technology. A packet communication control circuit supporting X.25-based layer 2 and 3 protocols, which was designed by this method, is presented.<<ETX>>