A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration

A 1.8GHz wideband fractional-N synthesizer achieves the phase noise of an integer-N PLL using a noise-cancellation DAC calibrated with an adaptive LMS spur correlation technique. It exhibits in-band and integrated phase noises of -98dBc/Hz and 0.8deg, respectively. The chip in 0.18mum CMOS occupies 2mm2, and consumes 29mW at 1.8V

[1]  R. Castello,et al.  A metal-oxide-semiconductor varactor , 1999, IEEE Electron Device Letters.

[2]  Jan Craninckx,et al.  A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-/spl mu/m CMOS , 1996 .

[3]  M. Steyaert,et al.  A fully integrated CMOS DCS-1800 frequency synthesizer , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[4]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[5]  Rinaldo Castello,et al.  An UMTS /spl Sigma//spl Delta/ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[6]  T. Riley,et al.  Delta-sigma modulation in fractional-N frequency synthesis , 1993 .

[7]  A. Hajimiri,et al.  Design issues in CMOS differential LC oscillators , 1999, IEEE J. Solid State Circuits.

[8]  Sudhakar Pamarti,et al.  Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[9]  W. Rhee,et al.  An on-chip phase compensation technique in fractional-N frequency synthesis , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[10]  B. Miller,et al.  A multiple modulator fractional divider , 1991 .

[11]  Lars C. Jansson,et al.  A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation , 2004, IEEE Journal of Solid-State Circuits.

[12]  A. Lacaita,et al.  A dual-band frequency synthesizer for 802.11a/b/g with fractional-spur averaging technique , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[13]  M. Steyaert,et al.  A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800 , 2002, IEEE J. Solid State Circuits.

[14]  Michael H. Perrott,et al.  A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation , 1997, IEEE J. Solid State Circuits.

[15]  John R. Long,et al.  Differentially driven symmetric microstrip inductors , 2002 .

[16]  D. Leeson.  A simple model of feedback oscillator noise spectrum , 1966 .

[17]  Scott E. Meninger,et al.  A fractional- N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise , 2003 .

[18]  A. Abidi,et al.  Physical processes of phase noise in differential LC oscillators , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[19]  Bram De Muer,et al.  On the analysis of ΔΣ fractional-N frequency synthesizers for high-spectral purity , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[20]  G. C. Gillette,et al.  Digiphase Synthesizer , 1969 .

[21]  C. Richard Johnson,et al.  Sign-sign LMS convergence with independent stochastic inputs , 1990, IEEE Trans. Inf. Theory.