Behaviour Driven Development for Hardware Design

Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers. Hence, one of the biggest challenges in design and verification today is to find new ways to increase the productivity. For software development the agile methodology as an incremental approach has been proposed and is heavily used. Behavior Driven Development (BDD) as an agile technique additionally enables a direct link to natural language based testing. In this article, we show how BDD can be extended to make it viable for hardware design. In addition, we present a two-fold strategy which allows to specify textual acceptance tests and textual formal properties. Finally, this strategy is complemented by methods to generalize tests to properties, and to enhance design understanding by presenting debug and witness scenarios in natural language.

[1]  Armin Biere,et al.  Bounded model checking , 2003, Adv. Comput..

[2]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[3]  Edmund M. Clarke,et al.  Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic , 1981, Logic of Programs.

[4]  Kavita Ravi,et al.  Minimal Assignments for Bounded Model Checking , 2004, TACAS.

[5]  George S. Avrunin,et al.  Patterns in property specifications for finite-state verification , 1999, Proceedings of the 1999 International Conference on Software Engineering (IEEE Cat. No.99CB37002).

[6]  Sandeep K. Shukla,et al.  XFM: An incremental methodology for developing formal models , 2005, TODE.

[7]  Rolf Drechsler,et al.  Behavior Driven Development for circuit design and verification , 2012, 2012 IEEE International High Level Design Validation and Test Workshop (HLDVT).

[8]  Martin Wirsing,et al.  Property-driven development , 2004, Proceedings of the Second International Conference on Software Engineering and Formal Methods, 2004. SEFM 2004..

[9]  Thomas A. Henzinger,et al.  Generating tests from counterexamples , 2004, Proceedings. 26th International Conference on Software Engineering.

[10]  Mary Sheeran,et al.  Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.

[11]  Dana Fisman,et al.  A Practical Introduction to PSL , 2006, Series on Integrated Circuits and Systems.

[12]  Rolf Drechsler,et al.  Behaviour Driven Development for Tests and Verification , 2014, TAP@STAF.

[13]  Markus M. Helms,et al.  An easy approach to formal verification , 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

[14]  Moshe Y. Vardi.  An Automata-Theoretic Approach to Linear Temporal Logic , 1996, Banff Higher Order Workshop.

[15]  Harry D. Foster.  Trends in functional verification: A 2014 industry study , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[16]  Jaco Geldenhuys,et al.  Cheap and Small Counterexamples , 2008, 2008 Sixth IEEE International Conference on Software Engineering and Formal Methods.

[17]  Amir Pnueli,et al.  The temporal logic of programs , 1977, 18th Annual Symposium on Foundations of Computer Science (sfcs 1977).

[18]  Sarfraz Khurshid,et al.  Test input generation with java PathFinder , 2004, ISSTA '04.

[19]  Rolf Drechsler,et al.  Finding good counter-examples to aid design verification , 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..

[20]  Thomas A. Henzinger,et al.  Extreme Model Checking , 2003, Verification: Theory and Practice.

[21]  Aaron R. Bradley,et al.  SAT-Based Model Checking without Unrolling , 2011, VMCAI.

[22]  D. Fisman,et al.  A Practical Introduction to PSL (Series on Integrated Circuits and Systems) , 2006 .

[23]  Brian Bailey,et al.  ESL Design and Verification: A Prescription for Electronic System Level Methodology , 2007 .

[24]  Edmund M. Clarke,et al.  Design and Synthesis of Synchronization Skeletons Using Branching Time Temporal Logic , 2008, 25 Years of Model Checking.

[25]  Matt Wynne,et al.  The Cucumber Book: Behaviour-Driven Development for Testers and Developers , 2012 .

[26]  Sandeep K. Shukla,et al.  Extreme formal modeling (XFM) for hardware models , 2004, Fifth International Workshop on Microprocessor Test and Verification (MTV'04).

[27]  George S. Avrunin,et al.  Property specification patterns for finite-state verification , 1998, FMSP '98.

[28]  John Pagonis.  The Ruby Programming Language... Ruby Programming Language... , 2009 .

[29]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[30]  Hubert Baumeister.  Combining Formal Specifications with Test Driven Development , 2004, XP/Agile Universe.

[31]  Alex Groce,et al.  What Went Wrong: Explaining Counterexamples , 2003, SPIN.

[32]  Edsger W. Dijkstra.  Finding the Maximum Strong Components in a Directed Graph , 1982 .

[33]  O.A. Mohamed,et al.  Automatic generation of model checking properties and constraints from production based specification , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[34]  Hans Eveking,et al.  Improving testbench evaluation using normalized formal properties , 2009 .

[35]  Edmund M. Clarke,et al.  Counterexample-guided abstraction refinement , 2003, 10th International Symposium on Temporal Representation and Reasoning, 2003 and Fourth International Conference on Temporal Logic. Proceedings..

[36]  André Sülflow.  WoLFram- A Word Level Framework for Formal Verification , 2009, 2009 IEEE/IFIP International Symposium on Rapid System Prototyping.

[37]  Seb Rose,et al.  The Cucumber for Java Book: Behaviour-Driven Development for Testers and Developers , 2015 .

[38]  Tommi Mikkonen,et al.  Supporting agile development by facilitating natural user interaction with executable formal specifications , 2011, SOEN.