Relation between stress-induced leakage current and time-dependent dielectric breakdown in ultra-thin gate oxides

The stress-induced leakage current (SILC) of a 4.2 nm SiO2 layer is investigated during constant gate voltage stress of metal-oxide-semiconductor capacitors. The density of bulk electron traps generated during the electrical stress is extracted from the SILC contribution, assuming a trap-assisted tunnelling mechanism. It is shown that a fixed critical value for the density of traps is reached at breakdown or soft breakdown of the SiO2 layer, independent of the gate voltage stress. A physical model based on the formation of a percolation path between the bulk electron traps randomly generated during the stress is proposed to link SILC to time-dependent dielectric breakdown in ultra-thin gate oxides. The validity of this model with respect to positive and negative stress polarities is discussed. It is also shown that this model allows us to predict the reliability of ultra-thin gate oxide layers at low applied gate voltage stress.

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