Efficient Power Network Analysis Considering Multidomain Clock Gating

In this paper, an efficient framework is proposed to analyze the worst case of voltage variation of power network considering multidomain clock gating. First, a frequency-domain-based simulation method is proposed to obtain the time-domain voltage response. With the vector fitting technique, the frequency-domain responses are approximated by a partial fraction expression, which can be easily converted to a time-domain waveform. Then, an algorithm is proposed to find the worst-case voltage variation and corresponding clock gating patterns, through superimposing the voltage responses caused by all domains working separately. The major computation of the whole framework is solving the frequency-domain equation system, whose complexity is about O(NalphaD log f max), where alpha is between one and two if using an iterative solver from the PETSc library. N is the node number, f max is the upper bound of frequency, and D is the number of clock domains. Numerical results show that the proposed simulation method is up to several hundred times faster than commercial fast simulators, like HSPICE and MSPICE. In addition, the proposed method is able to analyze large-scale power networks that the commercial tools are not able to afford.

[1]  Yici Cai,et al.  Partitioning-based approach to fast on-chip decap budgeting and minimization , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[2]  B. Gustavsen,et al.  Improving the pole relocating properties of vector fitting , 2006, 2006 IEEE Power Engineering Society General Meeting.

[3]  Ibrahim N. Hajj,et al.  Simulation and optimization of the power distribution network in VLSI circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[4]  Ekanathan Palamadai Natarajan,et al.  KLU{A HIGH PERFORMANCE SPARSE LINEAR SOLVER FOR CIRCUIT SIMULATION PROBLEMS , 2005 .

[5]  J. S. Neely,et al.  Interconnect and circuit modeling techniques for full-chip power supply noise analysis , 1998 .

[6]  Yiran Chen,et al.  Deterministic clock gating for microprocessor power reduction , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[7]  Sachin S. Sapatnekar,et al.  Analysis and optimization of structured power/ground networks , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Yici Cai,et al.  Efficient early stage resonance estimation techniques for C4 package , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[9]  Charlie Chung-Ping Chen,et al.  Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[10]  Rajeev Murgai,et al.  Fast power network analysis with multiple clock domains , 2007, 2007 25th International Conference on Computer Design.

[11]  Andrew T. Yang,et al.  Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[12]  Zhao Li,et al.  An efficiently preconditioned GMRES method for fast parasitic-sensitive deep-submicron VLSI circuit simulation , 2005, Design, Automation and Test in Europe.

[13]  Eby G. Friedman,et al.  Power Distribution Networks with On-Chip Decoupling Capacitors , 2007 .

[14]  Sani R. Nassif,et al.  Fast power grid simulation , 2000, Proceedings 37th Design Automation Conference.

[15]  A. Semlyen,et al.  Rational approximation of frequency domain responses by vector fitting , 1999 .