A CMOS 6 b 200 M sample/s 3 V-supply A/D converter for a PRML read channel LSI

There is a strong demand for high speed ADCs for PRML read channel LSI. Most of these ADCs are fabricated with bipolar or BiCMOS, because of high-speed operation. Conventional CMOS ADCs have 100 MSample/s conversion rate and insufficient tolerance to power supply noise. These problems are overcome by interleaved auto-zeroing (IAZ) architecture and output-swing limiting comparator (OLC). The ADCs operate at 200 MSample/s in a mixed PRML read channel LSI.

[1]  M.-F. Keiko,et al.  Measurement of digital noise in mixed-signal integrated circuits , 1993, Symposium 1993 on VLSI Circuits.

[2]  Toshio Kumamoto,et al.  A 10 bit 20 MS/s 3 V supply CMOS A/D converter , 1994 .

[3]  Jieh-Tsorng Wu,et al.  A 100-MHz pipelined CMOS comparator , 1988 .

[4]  Michiel Steyaert,et al.  A 100 MHz 8 bit CMOS interpolating A/D converter , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.