Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

In this paper, a new concept which allows the reduction of test vectors volume is presented. The concept is based on reconfiguration of some gates of circuit under test. Instead of testing the original circuit, a circuit which has the same topology (but some of its gate functions are reconfigured) is actually tested. Two possible implementations of the reconfiguration are investigated. Preliminary experiments indicate that test length can be reduced to approx. 70% of its initial value while the increase in transistors is moderate.

[1]  Alex Orailoglu,et al.  Property-based testability analysis for hierarchical RTL designs , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[2]  Adrian Stoica,et al.  Polymorphic Electronics , 2001, ICES.

[3]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[4]  Wen-Ben Jone,et al.  Fault simulation and response compaction in full scan circuits using HOPE , 2005, IEEE Transactions on Instrumentation and Measurement.

[5]  Janak H. Patel,et al.  Partial scan design based on circuit state information and functional analysis , 2004, IEEE Transactions on Computers.

[6]  Aristides Efthymiou,et al.  Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Nur A. Touba,et al.  Low power test data compression based on LFSR reseeding , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[8]  Irith Pomeranz,et al.  Static test compaction for multiple full-scan circuits , 2003, Proceedings 21st International Conference on Computer Design.

[9]  Adrian Stoica,et al.  On Polymorphic Circuits and Their Design Using Evolutionary Algorithms , 2002 .

[10]  Sungju Park.  A partial scan design unifying structural analysis and testabilities , 2001 .

[11]  Xin Guo,et al.  Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration , 2004 .