Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

This paper illustrates the growing significance of self and mutual inductances by examining their effects on performance and characteristic issues like propagation delay, rise time, and overshoots. This paper introduces Elmore-like closed form solutions to analyze the behavior of integrated circuits in the presence of self and mutual inductances. The complexity of the expressions introduced here is linear with the number of elements in the interconnect network, and has Elmore delay accuracy characteristics. The propagation delay and overshoots estimated based on these formulae are within 15% of AS/X simulations for a wide range of interconnects from IBM's most recent CMOS technology.

[1]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[2]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[3]  George Papadopoulos,et al.  Full-wave PEEC time-domain method for the modeling of on-chipinterconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  E. Friedman,et al.  Equivalent Elmore delay for RLC trees , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[5]  David Blaauw,et al.  Inductance 101: analysis and design issues , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[6]  Shannon V. Morton,et al.  On-chip inductance issues in multiconductor systems , 1999, DAC '99.

[7]  A. Deutsch,et al.  The importance of inductance and inductive coupling for on-chip wiring , 1997, Electrical Performance of Electronic Packaging.

[8]  Yehea Ismail,et al.  Figures of merit to characterize the importance of on-chip inductance , 1999 .

[9]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[10]  Keith A. Jenkins,et al.  When are transmission-line effects important for on-chip interconnections? , 1997 .

[11]  Daniel C. Edelstein,et al.  On-chip wiring design challenges for gigahertz operation , 2001, Proc. IEEE.

[12]  Chandramouli V. Kashyap,et al.  A realizable driving point model for on-chip interconnect with inductance , 2000, Proceedings 37th Design Automation Conference.

[13]  Denis B. Jarvis The Effects of Interconnections on High-Speed Logic Circuits , 1963, IEEE Trans. Electron. Comput..

[14]  K.C. Saraswat,et al.  Effect of scaling of interconnections on the time delay of VLSI circuits , 1982, IEEE Transactions on Electron Devices.

[15]  Griff L. Bilbro,et al.  Improved delay prediction for on-chip buses , 1999, DAC '99.

[16]  Yehea I. Ismail,et al.  Equivalent Elmore delay for RLC trees , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..