An optimized VLSI architecture for a multiformat discrete cosine transform

This communication presents an optimized architecture providing the computation power and the versatility that are required for the real-time processing of various blocks format (from 4*4 to 16*16) and for direct/inverse Discrete Cosine Transform. To achieve a realistic single chip implementation, different architectures have been compared. Circuits based on the most efficient architecture will be used for a real-time coder/decoder of color images.