A tampering protocol for reducing the coherence transactions in regular computation

This paper proposes a tampering protocol for reducing the coherence transactions in the computations with regular communication patterns. This protocol is a subsidiary of the conventional cache-coherence protocol and is activated on a memory-block basis. If activated for a block, the exclusive copy of that block is frozen in the cache and is accessed (i.e., tampered) with no coherence transactions; otherwise, the coherency is maintained by the conventional protocol. Thus by activating the tampering protocol for the shared data of processes, the latency of communication between the processes reduces. As a by-product, the stream data are effectively implemented with the tampering protocol. The effects of the tampering protocol on the regular computations are evaluated by an RTL simulator of our multiprocessor. The result shows that the tampering protocol greatly improves the performance with a conventional protocol. Then the stream is effective for the process synchronization.

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