An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming

This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the “SPICE accuracy” device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.

[1]  Chih-Kong Ken Yang,et al.  Device-circuit co-optimization for mixed-mode circuit design via geometric programming , 2007, ICCAD 2007.

[2]  Stephen P. Boyd,et al.  Optimal design of a CMOS op-amp via geometric programming , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Stephen P. Boyd,et al.  Convex Optimization , 2004, Algorithms and Theory of Computation Handbook.

[4]  Evangeline F. Y. Young,et al.  Analog Placement with Symmetry and Other Placement Constraints , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[5]  Georges G. E. Gielen,et al.  Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Denis Flandre,et al.  A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA , 1996, IEEE J. Solid State Circuits.

[7]  A.L. Sangiovanni-Vincentelli,et al.  A survey of optimization techniques for integrated-circuit design , 1981, Proceedings of the IEEE.

[8]  Ka Nang Leung,et al.  Analysis of low-dropout regulator topologies for low-voltage regulation , 2003, 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668).

[9]  E. Sanchez-Sinencio,et al.  Single Miller capacitor frequency compensation technique for low-power multistage amplifiers , 2005, IEEE Journal of Solid-State Circuits.

[10]  Shyh-Chang Lin,et al.  Analog Placement Based on Novel Symmetry-Island Formulation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[11]  E. Charbon,et al.  A Constraint-driven Placement Methodology For Analog Integrated Circuits , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[12]  Florin Balasa,et al.  Module placement for analog layout using the sequence-pair representation , 1999, DAC '99.

[13]  Pradip Mandal,et al.  An automated design approach for CMOS LDO regulators , 2009, 2009 Asia and South Pacific Design Automation Conference.

[14]  Stephen P. Boyd,et al.  Optimization of inductor circuits via geometric programming , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[15]  Yao-Wen Chang,et al.  MB$^{\ast}$-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Gabriel A. Rincon-Mora,et al.  Study and Design of Low Drop-Out Regulators , 2002 .

[17]  W. Daems,et al.  An efficient optimization-based technique to generate posynomial performance models for analog integrated circuits , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[18]  Shyh-Chang Lin,et al.  Analog placement based on hierarchical module clustering , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[19]  J. Shewchuk.  An Introduction to the Conjugate Gradient Method Without the Agonizing Pain , 1994 .

[20]  Chih-Kong Ken Yang,et al.  Techniques for improving the accuracy of geometric-programming based analog circuit design optimization , 2004, ICCAD 2004.

[21]  Georges G. E. Gielen,et al.  Generalized posynomial performance modeling , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[22]  Domine Leenaerts,et al.  DARWIN: CMOS opamp Synthesis by Means of a Genetic Algorithm , 1995, 32nd Design Automation Conference.