On the Limitations of Analyzing Worst-Case Dynamic Energy of Processing

This article examines dynamic energy consumption caused by data during software execution on deeply embedded microprocessors, which can be significant on some devices. In worst-case energy consumption analysis, energy models are used to find the most costly execution path. Taking each instruction’s worst-case energy produces a safe but overly pessimistic upper bound. Algorithms for safe and tight bounds would be desirable. We show that finding exact worst-case energy is NP-hard, and that tight bounds cannot be approximated with guaranteed safety. We conclude that any energy model targeting tightness must either sacrifice safety or accept overapproximation proportional to data-dependent energy.

[1]  William I. Gasarch Review of The Satisfiability Problem: Algorithms and Analyses by Uwe Schöning and Jacobo Torán , 2014, SIGA.

[2]  Tullio Vardanega,et al.  Upper-bounding Program Execution Time with Extreme Value Theory , 2013, WCET.

[3]  Kerstin Eder,et al.  Data dependent energy modelling: A worst case perspective , 2015, ArXiv.

[4]  Takeo Kanade,et al.  Static Analysis , 2014, Lecture Notes in Computer Science.

[5]  Christoforos E. Kozyrakis,et al.  A Comparison of High-Level Full-System Power Models , 2008, HotPower.

[6]  Neil W. Bergmann,et al.  Performance Evaluation of Asynchronous Logic Piplelines with Data Dependant , 1995 .

[7]  Sourav Roy,et al.  Estimation of energy consumed by software in processor caches , 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[8]  Paulo Francisco Butzen,et al.  Leakage Current in Sub-Micrometer CMOS Gates , 2008 .

[9]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[10]  Anantha Chandrakasan,et al.  Energy aware software , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[11]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, Proceedings of 9th International Conference on VLSI Design.

[12]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach (4. ed.) , 2007 .

[13]  Vijay V. Vazirani,et al.  Approximation Algorithms , 2001, Springer Berlin Heidelberg.

[14]  David S. Johnson,et al.  Approximation algorithms for combinatorial problems , 1973, STOC.

[15]  David May,et al.  The XMOS XS1 Architecture , 2009 .

[16]  Vincenzo Catania,et al.  An Instruction-Level Power Analysis Model with Data Dependency , 2001, VLSI Design.

[17]  Andrew Wolfe,et al.  Power Analysis Of Embedded Software: A First Step Towards Software Power Minimization , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[18]  Kerstin Eder,et al.  Energy Modeling of Software for a Hardware Multithreaded Embedded Microprocessor , 2015, ACM Trans. Embed. Comput. Syst..

[19]  Per Stenström,et al.  Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[20]  Michael S. Hsiao,et al.  K2: an estimator for peak sustainable power of VLSI circuits , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[21]  Kerstin Eder,et al.  Static analysis of energy consumption for LLVM IR programs , 2014, SCOPES.

[22]  Peter Marwedel,et al.  An Accurate and Fine Grain Instruction-Level Energy Model Supporting Software Optimizations , 2007 .

[23]  Toby Walsh,et al.  Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications , 2009 .

[24]  F. Longin,et al.  Extreme Events in Finance : A Handbook of Extreme Value Theory and Its Applications , 2016 .

[25]  Xianfeng Li,et al.  Estimating the Worst-Case Energy Consumption of Embedded Software , 2006, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06).

[26]  Gernot Heiser,et al.  An Analysis of Power Consumption in a Smartphone , 2010, USENIX Annual Technical Conference.

[27]  Kerstin Eder,et al.  Energy Transparency for Deeply Embedded Programs , 2017, ACM Trans. Archit. Code Optim..

[28]  Kerstin Eder,et al.  On the Value and Limits of Multi-level Energy Consumption Static Analysis for Deeply Embedded Single and Multi-threaded Programs , 2015, ArXiv.

[29]  Sharad Malik,et al.  Power analysis of embedded software: a first step towards software power minimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[30]  John P. Gallagher,et al.  Inferring Parametric Energy Consumption Functions at Different Software Levels: ISA vs. LLVM IR , 2015, FOPARA.

[31]  Manuel V. Hermenegildo,et al.  Energy Consumption Analysis of Programs Based on XMOS ISA-Level Models , 2013, LOPSTR.

[32]  Kerstin Eder,et al.  A high-level model of embedded flash energy consumption , 2014, 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).

[33]  David M. Brooks,et al.  Energy characterization and instruction-level energy model of Intel's Xeon Phi processor , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[34]  George Lima,et al.  Extreme Value Theory for Estimating Task Execution Time Bounds: A Careful Look , 2016, 2016 28th Euromicro Conference on Real-Time Systems (ECRTS).

[35]  Soontae Kim,et al.  DRAM energy reduction by prefetching-based memory traffic clustering , 2011, GLSVLSI '11.

[36]  Neil W. Bergmann,et al.  Performance evaluation of asynchronous logic pipelines with data dependent processing delays , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[37]  Kerstin Eder,et al.  Data Dependent Energy Modeling for Worst Case Energy Consumption Analysis , 2015, SCOPES.

[38]  Paulo F. Flores,et al.  Generating Realistic Stimuli for Accurate Power Grid Analysis , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[39]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[40]  Mahmut T. Kandemir,et al.  Instruction Scheduling for Low Power , 2004, J. VLSI Signal Process..

[41]  Kamran Rahmani,et al.  Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis , 2015, 2015 28th International Conference on VLSI Design.

[42]  Arlindo L. Oliveira,et al.  On The Complexity Of Power Estimation Problems , 2007 .

[43]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[44]  David A. Patterson,et al.  Computer Architecture, Fifth Edition: A Quantitative Approach , 2011 .

[45]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[46]  Lothar Thiele,et al.  Design for Timing Predictability , 2004, Real-Time Systems.

[47]  Tobias Distler,et al.  Worst-Case Energy Consumption Analysis for Energy-Constrained Embedded Systems , 2015, 2015 27th Euromicro Conference on Real-Time Systems.

[48]  Christoforos E. Kozyrakis,et al.  Understanding sources of inefficiency in general-purpose chips , 2010, ISCA.

[49]  Olivier Hudry Vijay V. Vazirani, "Approximation algorithms", Berlin-Heidelberg, Springer-Verlag, 2001 , 2003 .