A new approach for selecting inputs of logic functions during debug

Debugging logic functions involves finding the function of some of the internals nodes such that their functionality becomes correct, according to the given specification. In some cases, different new inputs are required for those internal nodes to be able to correct the functionality. In this paper, we propose an efficient method for selecting inputs of internal nodes during debug such that correction is guaranteed. Our method has a new different approach for debugging that focuses on finding the inputs of the functions without explicitly trying to find the new functions. This is done by iteratively solving SAT problems until we find the inputs. Our experimental results on ITC'99 benchmarks show the efficiency and effectiveness of our approach. The results show more than 30% reduction in the number of SAT problems to be solved as well as more than 85% reduction in debug time, on average, compared to the previous methods.

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