Weighing in on logic scaling trends

In this paper, scaling trends and the associated challenges are discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS) for both high-performance and low-power logic technologies. Starting from the overall chip circuit requirements, MOSFET and front-end process integration technology requirements, scaling trends, and challenges are discussed, as well as some of the key potential solutions to the challenges, along with the long-term issues and possible solutions for mobility improvement and optimal scaling for very small transistors. Potential solutions include eventual use of high-k gate dielectrics, metal gate electrodes, and perhaps nonclassical MOSFET devices such as double-gate SOI.

[1]  J. E. Brewer,et al.  Extending the road beyond CMOS , 2002 .

[2]  Qi Xiang,et al.  15 nm gate length planar CMOS transistor , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[3]  Peter Zeitzoff,et al.  Boron diffusion and activation in the presence of other species , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[4]  Gordon E. Moore,et al.  Lithography and the Future of Moore's Law, Copyright 1995 IEEE. Reprinted with permission. Proc. SPIE Vol. 2437, pp. 2–17 , 1995, IEEE Solid-State Circuits Newsletter.

[5]  M. Hussein,et al.  An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[6]  D. Reber,et al.  A high density 0.10 /spl mu/m CMOS technology using low K dielectric and copper interconnect , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[7]  K. Ng,et al.  The impact of intrinsic series resistance on MOSFET scaling , 1986, IEEE Transactions on Electron Devices.

[8]  James D. Plummer,et al.  The effect of source/drain processing on the reverse short channel effect of deep sub-micron bulk and SOI NMOSFETs , 1995, Proceedings of International Electron Devices Meeting.

[9]  Wei Jin,et al.  High performance 50 nm CMOS devices for microprocessor and embedded processor core applications , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[10]  W. P. Maszara,et al.  Very thin CoSi2 films by Co sputtering , 1993 .

[11]  P. K. Vasudev,et al.  Si-ULSI with a scaled down future , 1998 .

[12]  T. Ma,et al.  Tunneling leakage current in oxynitride: dependence on oxygen/nitrogen content , 1998, IEEE Electron Device Letters.

[13]  G. Bersuker,et al.  Conventional n-channel MOSFET devices using single layer HfO/sub 2/ and ZrO/sub 2/ as high-k gate dielectrics with polysilicon gate electrode , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[14]  P. A. Gargini.  The global route to future semiconductor technology , 2002 .

[15]  T. Mogami,et al.  High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

[16]  K. Onishi,et al.  Reliability characteristics, including NBTI, of polysilicon gate HfO/sub 2/ MOSFET's , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[17]  T. Kudo,et al.  High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).