Autometic Generation of SystemC Transactors from AsmL Specification

The SoC design flow consists of different levels of abstraction. At Transaction Level Modeling (TLM) different modules communicate with each other through function calls. In contrast, at the Register Transfer Level (RTL), different modules communicate through pin level signaling. The notion of transactors has been introduced recently in order to link modules (IP blocks) written at different levels of abstraction. A transactor can be modeled using a finite state machines (FSM) describing the functional protocol behaviors. In this paper, we propose to specify transactor behavior using the Abstract State Machine Language (AsmL). We also define a methodology and a tool that automatically generates SystemC TLM-RTL transactors from these AsmL specifications. The proposed approach has been implemented and applied on several case studies including an UTOPIA standard protocol.