A Novel High-Performance Leakage-Tolerant Keeper Domino Circuit for Wide Fan-In Gates

A circuit with less power consumption, the minimum amount of leakage, and least possible delay are the primary aim of the circuit designer. In this paper, a circuit exhibiting similar qualities is proposed. The proposed circuit works on the principle to diminish contention between the pull-down network (PDN) and the keeper, according to the leakage flowing across PDN; moreover, the diode-footed configuration aids in reducing circuit leakage current. 180 nm CMOS technology is used for simulation with 1.8 V supply voltage at 500 M clock frequency. The proposed circuit has reduced power consumption by 29% with improved energy efficiency compared to the standard footless domino. The result is verified with 180 nm CMOS technology TCAD EDA tools.