Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults

Due to the continuous shrinking of semiconductor technology, there are more and more variations in the process of manufacturing chips. From the viewpoint of analyzing the functionality of a chip, variation may change the overall "observed" behavior of the chip. In this paper, we discuss additional delays caused by variation that may generate changes of observed behaviors. In the first part of the paper, we discuss functional changes caused by additional delays on the inputs of each gate in the circuit. Unlike stuck-at faults, such additional delays can introduce many different faulty functions on a gate. For example, in the cases of two-input AND/OR gate, all possible logic functions with two-input, which are 222=16 different functions, can potentially be observed. This indicates that it may make sense to model faulty behaviors caused by variation as general functional faults rather than structurally defined faults, such as stuck-at faults. Also, such additional delays by variation can happen in multiple locations simultaneously. As a result, there can be so many possible fault combinations to be considered, and it is not easy at all to analyze them with traditional automatic test pattern generation (ATPG) methods which drop detectable faults by fault simulators using explicit representation of faults. So in the second part of the paper, we discuss about ATPG methods where test pattern generation and fault dropping processes are unified. As faults are represented implicitly, even if numbers of simultaneous faults are large, we may still be able to successfully perform ATPG processes.