A new 8V – 60V rated low Vgs NLDMOS structure with enhanced specific on-resistance

We present a new 0.35um BCDMOS technology with a capability of 8 to 60V NLDMOS. The proposed process do not need level shifter, charge pump and boost up due to the same gate oxide thickness with logic 5V CMOS. And the Rsp of the proposed 24V NLDMOS structure is lower by 46% than conventional structure. The process has no thermal budget modification but use simple additional implant step. Also it is compatible with the conventional BCDMOS. The power LDMOS transistors in the process have very competitive performances with NLDMOS in 0.15 - 0.25um BCDMOS technologies.

[1]  Il-Yong Park,et al.  Implementation of 85V High Side LDMOS with n-layer in a 0.35um BCD Process , 2008, 2008 20th International Symposium on Power Semiconductor Devices and IC's.

[2]  C. Contiero,et al.  BCD8 from 7V to 70V: a new 0.l8μm Technology Platform to Address the Evolution of Applications towards Smart Power ICs with High Logic Contents , 2007, Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's.

[3]  P. Deurenberg,et al.  55V Integrated Power and Non-Volatile Technology for Solid State Lighting Applications , 2008, 2008 20th International Symposium on Power Semiconductor Devices and IC's.

[4]  S. Maegawa,et al.  0.15µm BiC-DMOS technology with novel stepped-STI N-channel LDMOS , 2009, 2009 21st International Symposium on Power Semiconductor Devices & IC's.

[5]  Philip L. Hower Safe operating area - a new frontier in Ldmos design , 2002, Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics.