Bit serial fault tolerant architectures for convolution and polynomial evaluation

The authors present three distinct serial-input serial-output architectures: two for the computation of discrete convolution (bit-sliced and polyphase convolvers) and one for polynomial evaluation (polynomiers). These devices operate in serial fixed point natural arithmetic. All architectures are characterized by a bit-sliced structure that makes possible easy design and testing. The regular, uniform bit-slices also give the possibility of introducing functional reconfigurability and fault tolerance. For all these reasons, the proposed three architectures are good candidates for VLSI and WSI (wafer scale integration) implementation. Prototypal layouts, testing procedures, and statistical analysis have been developed for the evaluation of the architecture performances, the introduction of fault tolerance, and the study of the obtained fault coverage, reliability, and fabrication yield.<<ETX>>