SEE and TID Results for a RadHard-by-Design 16Mbit SRAM with Embedded EDAC

Radhard-by-design has been advanced by embedding EDAC into a 16Mbit SRAM to harden the SRAM against single event upset. Conventional radhard-by-design techniques are used for the non-memory circuitry. The estimated uncorrectable double bit error rate is 2.9 times 10-16 errors/bit-day assuming a geosynchronous orbit, the Adam's 90% worst case environment and a nominal 312 kHz scrub frequency. The device is SEL immune to a LET of 105 MeV-cm2/mg and TID hard to greater than 100 krad(Si)